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autoannotated the opcodes
2011-12-22 13:04:09 +08:00
<!-- Visit http://ref.x86asm.net/ -->
<!--
Author: Karel Lejska a.k.a. MazeGen (mazegen gmail com)
Short Description:
This reference is intended to be precise opcode and instruction
set reference (including x86-64). Its principal aim is exact
definition of instruction parameters and attributes.
- Minor Issues:
83/1, 83/4, 83/6:
These short forms of OR, AND, and XOR instructions are documented
since 80386. They were probably working since 8086, 80186
or 80286, but I have no trustworthy information regarding this issue.
D9/3 mod=11, DF/2 mod=11, DF/3 mod=11:
These encodings are documented in Intel 80287 manual at least. They
were probably working since 8086, 80186 or 80286, but I have no
trustworthy information regarding this issue.
0F0D:
I am not sure since which Intel procesor was second multi-byte NOP (0F0D)
released. The reference sets it since Pentium Pro.
0FAE /0 FXSAVE, 0FAE /1 FXRSTOR
Current Intel manuals say that these were introduced with PIII
processor. I can't find them documented in PIII manual though.
Because of this problem, these instructions are marked as introduced
with latter steppings of PIII processor.
- Discussion:
FF /3, FF /5:
Should I add this comment?
"The offset from the target operand is ignored when a call gate is used."
LAR, LSL:
Should I add this comment?
"For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are ignored."
-->
<x86reference version="1.11">
<one-byte>
<pri_opcd value="00">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>ADD</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="01">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>ADD</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="02">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>ADD</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="03">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>ADD</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="04">
<entry op_size="0" attr="acc">
<syntax>
<mnem>ADD</mnem>
<dst nr="0" group="gen" type="b">AL</dst>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="05">
<entry op_size="1" attr="acc">
<syntax><mnem>ADD</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="06">
<entry>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="0" group="seg" type="w" address="S2">ES</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="07">
<entry>
<syntax>
<mnem>POP</mnem>
<dst nr="0" group="seg" type="w" address="S2" depend="no">ES</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="08">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>OR</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="09">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>OR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="0A">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>OR</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="0B">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>OR</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="0C">
<entry op_size="0" attr="acc">
<syntax><mnem>OR</mnem><dst nr="0" group="gen" type="b">AL</dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="0D">
<entry op_size="1" attr="acc">
<syntax><mnem>OR</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="0E">
<entry>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="1" group="seg" type="w" address="S2">CS</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="0F">
<entry doc1632_ref="gen_note_opcd_POP_CS_0F">
<proc_start post="no">00</proc_start>
<proc_end>00</proc_end>
<syntax>
<mnem>POP</mnem>
<dst nr="1" group="seg" type="w" address="S2">CS</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
<entry attr="invd">
<proc_start post="no">01</proc_start>
<proc_end>01</proc_end>
<syntax/>
</entry>
<entry ref="two-byte">
<proc_start>02</proc_start>
<syntax/>
</entry>
</pri_opcd>
<pri_opcd value="10">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>ADC</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="11">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>ADC</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="12">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>ADC</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="13">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>ADC</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="14">
<entry op_size="0" attr="acc">
<syntax><mnem>ADC</mnem><dst nr="0" group="gen" type="b">AL</dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="15">
<entry op_size="1" attr="acc">
<syntax><mnem>ADC</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="16">
<entry>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="2" group="seg" type="w" address="S2">SS</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="17">
<entry attr="delaysint">
<syntax>
<mnem>POP</mnem>
<dst nr="2" group="seg" type="w" address="S2" depend="no">SS</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="18">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>SBB</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="19">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>SBB</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="1A">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>SBB</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="1B">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>SBB</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="1C">
<entry op_size="0" attr="acc">
<syntax><mnem>SBB</mnem><dst nr="0" group="gen" type="b">AL</dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="1D">
<entry op_size="1" attr="acc">
<syntax><mnem>SBB</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="1E">
<entry>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="3" group="seg" type="w" address="S2">DS</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="1F">
<entry>
<syntax>
<mnem>POP</mnem>
<dst nr="3" group="seg" type="w" address="S2" depend="no">DS</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="20">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>AND</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="21">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>AND</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="22">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>AND</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="23">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>AND</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="24">
<entry op_size="0" attr="acc">
<syntax><mnem>AND</mnem><dst nr="0" group="gen" type="b">AL</dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="25">
<entry op_size="1" attr="acc">
<syntax><mnem>AND</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="26">
<entry>
<syntax>
<mnem>ES</mnem>
<src nr="0" group="seg" type="w" displayed="no">ES</src>
</syntax>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>ES segment override prefix</brief></note>
</entry>
<entry attr="undef">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax/>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>(use with any branch instruction is reserved)</brief></note>
</entry>
<entry attr="null" mode="e">
<proc_start>10</proc_start>
<syntax/>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>Null Prefix in 64-bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="27">
<entry>
<syntax>
<mnem>DAA</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<test_f>ac</test_f><modif_f>oszapc</modif_f><def_f>szapc</def_f><undef_f>o</undef_f>
<note><brief>Decimal Adjust AL after Addition</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="28">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>SUB</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="29">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>SUB</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2A">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>SUB</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2B">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>SUB</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2C">
<entry op_size="0" attr="acc">
<syntax><mnem>SUB</mnem><dst nr="0" group="gen" type="b">AL</dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2D">
<entry op_size="1" attr="acc">
<syntax><mnem>SUB</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2E">
<entry>
<syntax>
<mnem>CS</mnem>
<src nr="1" group="seg" type="w" displayed="no">CS</src>
</syntax>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>CS segment override prefix</brief></note>
</entry>
<entry doc1632_ref="gen_note_branch_prefixes">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax><mnem sug="yes">NTAKEN</mnem></syntax>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Branch not taken prefix (only with Jcc instructions)</brief></note>
</entry>
<entry attr="null" mode="e">
<proc_start>10</proc_start>
<syntax/>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>Null Prefix in 64-bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2F">
<entry>
<syntax>
<mnem>DAS</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<test_f>ac</test_f><modif_f>oszapc</modif_f><def_f>szapc</def_f><undef_f>o</undef_f>
<note><brief>Decimal Adjust AL after Subtraction</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="30">
<entry direction="0" op_size="0" r="yes" lock="yes">
<syntax><mnem>XOR</mnem><dst><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="31">
<entry direction="0" op_size="1" r="yes" lock="yes">
<syntax><mnem>XOR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="32">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>XOR</mnem><dst><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="33">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>XOR</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="34">
<entry op_size="0" attr="acc">
<syntax><mnem>XOR</mnem><dst nr="0" group="gen" type="b">AL</dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="35">
<entry op_size="1" attr="acc">
<syntax><mnem>XOR</mnem><dst nr="0" group="gen" type="vqp">rAX</dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="36">
<entry>
<syntax>
<mnem>SS</mnem>
<src nr="2" group="seg" type="w" displayed="no">SS</src>
</syntax>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>SS segment override prefix</brief></note>
</entry>
<entry attr="undef">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax/>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>(use with any branch instruction is reserved)</brief></note>
</entry>
<entry attr="null" mode="e">
<proc_start>10</proc_start>
<syntax/>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>Null Prefix in 64-bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="37">
<entry>
<syntax>
<mnem>AAA</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no">AH</dst>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<test_f>a</test_f><modif_f>oszapc</modif_f><def_f>ac</def_f><undef_f>oszp</undef_f>
<note><brief>ASCII Adjust After Addition</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="38">
<entry direction="0" op_size="0" r="yes">
<syntax><mnem>CMP</mnem><src><a>E</a><t>b</t></src><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="39">
<entry direction="0" op_size="1" r="yes">
<syntax><mnem>CMP</mnem><src><a>E</a><t>vqp</t></src><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="3A">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>CMP</mnem><src><a>G</a><t>b</t></src><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="3B">
<entry direction="1" op_size="1" r="yes">
<syntax><mnem>CMP</mnem><src><a>G</a><t>vqp</t></src><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="3C">
<entry op_size="0" attr="acc">
<syntax><mnem>CMP</mnem><src nr="0" group="gen" type="b">AL</src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="3D">
<entry op_size="1" attr="acc">
<syntax><mnem>CMP</mnem><src nr="0" group="gen" type="vqp">rAX</src><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="3E">
<entry>
<syntax>
<mnem>DS</mnem>
<src nr="3" group="seg" type="w" displayed="no">DS</src>
</syntax>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>DS segment override prefix</brief></note>
</entry>
<entry doc1632_ref="gen_note_branch_prefixes">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax><mnem sug="yes">TAKEN</mnem></syntax>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Branch taken prefix (only with Jcc instructions)</brief></note>
</entry>
<entry attr="null" mode="e">
<proc_start>10</proc_start>
<syntax/>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>Null Prefix in 64-bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="3F">
<entry>
<syntax>
<mnem>AAS</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no">AH</dst>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<test_f>a</test_f><modif_f>oszapc</modif_f><def_f>ac</def_f><undef_f>oszp</undef_f>
<note><brief>ASCII Adjust AL After Subtraction</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="40">
<entry>
<syntax><mnem>INC</mnem><dst><a>Z</a><t>v</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszap</modif_f><def_f>oszap</def_f>
<note><brief>Increment by 1</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>Access to new 8-bit registers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="41">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.B</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>Extension of r/m field, base field, or opcode reg field</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="42">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.X</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>Extension of SIB index field</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="43">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.XB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.X and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="44">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.R</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>Extension of ModR/M reg field</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="45">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.RB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.R and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="46">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.RX</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.R and REX.X combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="47">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.RXB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.R, REX.X and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="48">
<entry>
<syntax><mnem>DEC</mnem><dst><a>Z</a><t>v</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszap</modif_f><def_f>oszap</def_f>
<note><brief>Decrement by 1</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.W</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>64 Bit Operand Size</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="49">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4A">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WX</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W and REX.X combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4B">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WXB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W, REX.X and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4C">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WR</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W and REX.R combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4D">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WRB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W, REX.R and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4E">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WRX</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W, REX.R and REX.X combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4F">
<entry mode="e">
<proc_start>10</proc_start>
<syntax><mnem>REX.WRXB</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>REX.W, REX.R, REX.X and REX.B combination</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="50">
<entry>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>Z</a><t>v</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>Z</a><t>vq</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="58">
<entry>
<syntax>
<mnem>POP</mnem>
<dst depend="no"><a>Z</a><t>v</t></dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>POP</mnem>
<dst depend="no"><a>Z</a><t>vq</t></dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="60">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>PUSHA</mnem>
<!-- 1.02
<src nr="0" group="gen" type="w" displayed="no">AX</src>
<src nr="1" group="gen" type="w" displayed="no">CX</src>
<src nr="2" group="gen" type="w" displayed="no">DX</src>
<src nr="3" group="gen" type="w" displayed="no">BX</src>
<src nr="4" group="gen" type="w" displayed="no">SP</src>
<src nr="5" group="gen" type="w" displayed="no">BP</src>
<src nr="6" group="gen" type="w" displayed="no">SI</src>
<src nr="7" group="gen" type="w" displayed="no">DI</src>
-->
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
<src nr="1" group="gen" type="wo" displayed="no">CX</src>
<src nr="2" group="gen" type="wo" displayed="no">DX</src>
<src nr="3" group="gen" type="wo" displayed="no">BX</src>
<src nr="4" group="gen" type="wo" displayed="no">SP</src>
<src nr="5" group="gen" type="wo" displayed="no">BP</src>
<src nr="6" group="gen" type="wo" displayed="no">SI</src>
<src nr="7" group="gen" type="wo" displayed="no">DI</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push All General-Purpose Registers</brief></note>
</entry>
<entry>
<proc_start>03</proc_start>
<!-- duplicated syntax removed in 1.02
<syntax>
<mnem>PUSHA</mnem>
<src nr="0" group="gen" type="w" displayed="no">AX</src>
<src nr="1" group="gen" type="w" displayed="no">CX</src>
<src nr="2" group="gen" type="w" displayed="no">DX</src>
<src nr="3" group="gen" type="w" displayed="no">BX</src>
<src nr="4" group="gen" type="w" displayed="no">SP</src>
<src nr="5" group="gen" type="w" displayed="no">BP</src>
<src nr="6" group="gen" type="w" displayed="no">SI</src>
<src nr="7" group="gen" type="w" displayed="no">DI</src>
</syntax>
-->
<syntax>
<mnem>PUSHAD</mnem>
<!-- 1.02
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
<src nr="3" group="gen" type="d" displayed="no">EBX</src>
<src nr="4" group="gen" type="d" displayed="no">ESP</src>
<src nr="5" group="gen" type="d" displayed="no">EBP</src>
<src nr="6" group="gen" type="d" displayed="no">ESI</src>
<src nr="7" group="gen" type="d" displayed="no">EDI</src>
-->
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
<src nr="1" group="gen" type="do" displayed="no">ECX</src>
<src nr="2" group="gen" type="do" displayed="no">EDX</src>
<src nr="3" group="gen" type="do" displayed="no">EBX</src>
<src nr="4" group="gen" type="do" displayed="no">ESP</src>
<src nr="5" group="gen" type="do" displayed="no">EBP</src>
<src nr="6" group="gen" type="do" displayed="no">ESI</src>
<src nr="7" group="gen" type="do" displayed="no">EDI</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push All General-Purpose Registers</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="61">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>POPA</mnem>
<!-- 1.02
<dst nr="7" group="gen" type="w" displayed="no">DI</dst>
<dst nr="6" group="gen" type="w" displayed="no">SI</dst>
<dst nr="5" group="gen" type="w" displayed="no">BP</dst>
<dst nr="3" group="gen" type="w" displayed="no">BX</dst>
<dst nr="2" group="gen" type="w" displayed="no">DX</dst>
<dst nr="1" group="gen" type="w" displayed="no">CX</dst>
<dst nr="0" group="gen" type="w" displayed="no">AX</dst>
-->
<dst nr="7" group="gen" type="wo" displayed="no">DI</dst>
<dst nr="6" group="gen" type="wo" displayed="no">SI</dst>
<dst nr="5" group="gen" type="wo" displayed="no">BP</dst>
<dst nr="3" group="gen" type="wo" displayed="no">BX</dst>
<dst nr="2" group="gen" type="wo" displayed="no">DX</dst>
<dst nr="1" group="gen" type="wo" displayed="no">CX</dst>
<dst nr="0" group="gen" type="wo" displayed="no">AX</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Pop All General-Purpose Registers</brief></note>
</entry>
<entry>
<proc_start>03</proc_start>
<!-- duplicated syntax removed in 1.02
<syntax>
<mnem>POPA</mnem>
<dst nr="7" group="gen" type="w" displayed="no">DI</dst>
<dst nr="6" group="gen" type="w" displayed="no">SI</dst>
<dst nr="5" group="gen" type="w" displayed="no">BP</dst>
<dst nr="3" group="gen" type="w" displayed="no">BX</dst>
<dst nr="2" group="gen" type="w" displayed="no">DX</dst>
<dst nr="1" group="gen" type="w" displayed="no">CX</dst>
<dst nr="0" group="gen" type="w" displayed="no">AX</dst>
</syntax>
-->
<syntax>
<mnem>POPAD</mnem>
<!-- 1.02
<dst nr="7" group="gen" type="d" displayed="no">EDI</dst>
<dst nr="6" group="gen" type="d" displayed="no">ESI</dst>
<dst nr="5" group="gen" type="d" displayed="no">EBP</dst>
<dst nr="3" group="gen" type="d" displayed="no">EBX</dst>
<dst nr="2" group="gen" type="d" displayed="no">EDX</dst>
<dst nr="1" group="gen" type="d" displayed="no">ECX</dst>
<dst nr="0" group="gen" type="d" displayed="no">EAX</dst>
-->
<dst nr="7" group="gen" type="do" displayed="no">EDI</dst>
<dst nr="6" group="gen" type="do" displayed="no">ESI</dst>
<dst nr="5" group="gen" type="do" displayed="no">EBP</dst>
<dst nr="3" group="gen" type="do" displayed="no">EBX</dst>
<dst nr="2" group="gen" type="do" displayed="no">EDX</dst>
<dst nr="1" group="gen" type="do" displayed="no">ECX</dst>
<dst nr="0" group="gen" type="do" displayed="no">EAX</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Pop All General-Purpose Registers</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="62">
<!--<entry direction="1" r="yes" mod="mem" ring="f">-->
<entry direction="1" r="yes" ring="f">
<proc_start>01</proc_start>
<syntax>
<mnem>BOUND</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>G</a><t>v</t></src>
<src><a>M</a><t>a</t></src>
<src type="v" address="F" displayed="no">eFlags</src>
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<modif_f cond="yes">i</modif_f>
<def_f cond="yes">i</def_f>
<f_vals>i</f_vals>
<note><brief>Check Array Index Against Bounds</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="63">
<entry r="yes">
<proc_start>02</proc_start>
<syntax><mnem>ARPL</mnem><src><a>E</a><t>w</t></src><src><a>G</a><t>w</t></src></syntax>
<grp1>system</grp1>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Adjust RPL Field of Segment Selector</brief></note>
</entry>
<entry direction="1" r="yes" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>MOVSXD</mnem>
<dst depend="no"><a>G</a><t>dqp</t></dst>
<!--<src><a>E</a><t>ds</t></src> 1.01 fix-->
<src><a>E</a><t>d</t></src>
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Move with Sign-Extension</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="64">
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>FS</mnem>
<src nr="4" group="seg" type="w" displayed="no">FS</src>
</syntax>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>FS segment override prefix</brief></note>
</entry>
<entry attr="undef" is_undoc="yes">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax/>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>(only with Jcc instructions)</brief></note>
</entry>
<entry doc="u" is_doc="yes" doc1632_ref="gen_note_branch_prefixes" particular="yes">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax>
<mnem sug="yes">ALTER</mnem>
</syntax>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Alternating branch prefix (only with Jcc instructions)</brief></note>
</entry>
<!-- 1.02
<entry attr="undef" mode="e">
<proc_start>10</proc_start>
<syntax/>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>(branch hint prefixes have no effect in 64-bit mode)</brief></note>
</entry>
-->
</pri_opcd>
<pri_opcd value="65">
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>GS</mnem>
<src nr="5" group="seg" type="w" displayed="no">GS</src>
</syntax>
<grp1>prefix</grp1><grp2>segreg</grp2>
<note><brief>GS segment override prefix</brief></note>
</entry>
<entry attr="undef">
<proc_start post="no">10</proc_start>
<proc_end>10</proc_end>
<syntax/>
<grp1>prefix</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>(only with Jcc instructions)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="66">
<entry>
<syntax/>
<grp1>prefix</grp1>
<note><brief>Operand-size override prefix</brief></note>
</entry>
<entry doc="m">
<proc_start>10</proc_start>
<syntax/>
<instr_ext>sse2</instr_ext>
<grp1>prefix</grp1>
<note><brief>Precision-size override prefix</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="67">
<entry>
<syntax/>
<grp1>prefix</grp1>
<note><brief>Address-size override prefix</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="68">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>I</a><t>vs</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="69">
<entry r="yes">
<proc_start>01</proc_start>
<syntax>
<mnem>IMUL</mnem>
<dst><a>G</a><t>vqp</t></dst>
<src><a>E</a><t>vqp</t></src>
<src><a>I</a><t>vds</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Signed Multiply</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6A">
<entry sign-ext="1">
<proc_start>01</proc_start>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>I</a><t>bss</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6B">
<entry sign-ext="1" r="yes">
<proc_start>01</proc_start>
<syntax>
<mnem>IMUL</mnem>
<dst><a>G</a><t>vqp</t></dst>
<src><a>E</a><t>vqp</t></src>
<src><a>I</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Signed Multiply</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6C">
<entry op_size="0" ring="f" ring_ref="rflags_iopl">
<proc_start>01</proc_start>
<syntax>
<mnem>INS</mnem>
<!--<dst depend="no"><a>Y</a><t>b</t></dst> 1.02-->
<dst type="b" address="Y" depend="no">(ES:)[rDI]</dst>
<src nr="2" group="gen" type="w">DX</src>
</syntax>
<syntax>
<mnem>INSB</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>b</t></dst> 1.02-->
<dst type="b" address="Y" displayed="no" depend="no">(ES:)[rDI]</dst>
<src nr="2" group="gen" type="w" displayed="no">DX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Input from Port to String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6D">
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<proc_start>01</proc_start>
<syntax>
<mnem>INS</mnem>
<!--<dst depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" depend="no">ES:[DI]</dst>
<src nr="2" group="gen" type="w">DX</src>
</syntax>
<syntax>
<mnem>INSW</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" displayed="no" depend="no">ES:[DI]</dst>
<src nr="2" group="gen" type="w" displayed="no">DX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Input from Port to String</brief></note>
</entry>
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<proc_start>03</proc_start>
<syntax>
<mnem>INS</mnem>
<!--<dst depend="no"><a>Y</a><t>v</t></dst> 1.02-->
<dst type="v" address="Y" depend="no">(ES:)[rDI]</dst>
<src nr="2" group="gen" type="w">DX</src>
</syntax>
<syntax>
<mnem>INSD</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>d</t></dst> 1.02-->
<dst type="do" address="Y" displayed="no" depend="no">(ES:)[rDI]</dst>
<src nr="2" group="gen" type="w" displayed="no">DX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Input from Port to String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6E">
<entry op_size="0" ring="f" ring_ref="rflags_iopl">
<proc_start>01</proc_start>
<syntax>
<mnem>OUTS</mnem>
<dst nr="2" group="gen" type="w" depend="no">DX</dst>
<!--<src><a>X</a><t>b</t></src> changed in 1.02-->
<src type="b" address="X">(DS):[rSI]</src>
</syntax>
<syntax>
<mnem>OUTSB</mnem>
<dst nr="2" group="gen" type="w" displayed="no" depend="no">DX</dst>
<!--<src displayed="no"><a>X</a><t>b</t></src> changed in 1.02-->
<src type="b" address="X" displayed="no">(DS):[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Output String to Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6F">
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<proc_start>01</proc_start>
<syntax>
<mnem>OUTS</mnem>
<dst nr="2" group="gen" type="w" depend="no">DX</dst>
<!--<src><a>X</a><t>w</t></src> changed in 1.02-->
<src type="wo" address="X">DS:[SI]</src>
</syntax>
<syntax>
<mnem>OUTSW</mnem>
<dst nr="2" group="gen" type="w" displayed="no" depend="no">DX</dst>
<!--<src displayed="no"><a>X</a><t>w</t></src> changed in 1.02-->
<src type="wo" address="X" displayed="no">DS:[SI]</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Output String to Port</brief></note>
</entry>
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<proc_start>03</proc_start>
<syntax>
<mnem>OUTS</mnem>
<dst nr="2" group="gen" type="w" depend="no">DX</dst>
<!--<src><a>X</a><t>v</t></src> changed in 1.02-->
<src type="v" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>OUTSD</mnem>
<dst nr="2" group="gen" type="w" displayed="no" depend="no">DX</dst>
<!--<src displayed="no"><a>X</a><t>d</t></src> changed in 1.02-->
<src type="do" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Output String to Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="70">
<entry tttn="0000">
<syntax><mnem>JO</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>o</test_f>
<note><brief>Jump short if overflow (OF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="71">
<entry tttn="0001">
<syntax><mnem>JNO</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>o</test_f>
<note><brief>Jump short if not overflow (OF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="72">
<entry tttn="0010">
<syntax><mnem>JB</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JNAE</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JC</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>c</test_f>
<note><brief>Jump short if below/not above or equal/carry (CF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="73">
<entry tttn="0011">
<syntax><mnem>JNB</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JAE</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JNC</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>c</test_f>
<note><brief>Jump short if not below/above or equal/not carry (CF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="74">
<entry tttn="0100">
<syntax><mnem>JZ</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JE</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Jump short if zero/equal (ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="75">
<entry tttn="0101">
<syntax><mnem>JNZ</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JNE</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Jump short if not zero/not equal (ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="76">
<entry tttn="0110">
<syntax><mnem>JBE</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JNA</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Jump short if below or equal/not above (CF=1 AND ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="77">
<entry tttn="0111">
<syntax><mnem>JNBE</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JA</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Jump short if not below or equal/above (CF=0 AND ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="78">
<entry tttn="1000">
<syntax><mnem>JS</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>s</test_f>
<note><brief>Jump short if sign (SF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="79">
<entry tttn="1001">
<syntax><mnem>JNS</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>s</test_f>
<note><brief>Jump short if not sign (SF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7A">
<entry tttn="1010">
<syntax><mnem>JP</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JPE</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>p</test_f>
<note><brief>Jump short if parity/parity even (PF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7B">
<entry tttn="1011">
<syntax><mnem>JNP</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JPO</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>p</test_f>
<note><brief>Jump short if not parity/parity odd</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7C">
<entry tttn="1100">
<syntax><mnem>JL</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JNGE</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>os</test_f>
<note><brief>Jump short if less/not greater (SF!=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7D">
<entry tttn="1101">
<syntax><mnem>JNL</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JGE</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>os</test_f>
<note><brief>Jump short if not less/greater or equal (SF=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7E">
<entry tttn="1110">
<syntax><mnem>JLE</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JNG</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>osz</test_f>
<note><brief>Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7F">
<entry tttn="1111">
<syntax><mnem>JNLE</mnem><src><a>J</a><t>bs</t></src></syntax>
<syntax><mnem>JG</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>osz</test_f>
<note><brief>Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="80">
<entry op_size="0" lock="yes">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ADD</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
<entry op_size="0" lock="yes">
<opcd_ext>1</opcd_ext>
<syntax><mnem>OR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
<entry op_size="0" lock="yes">
<opcd_ext>2</opcd_ext>
<syntax><mnem>ADC</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
<entry op_size="0" lock="yes">
<opcd_ext>3</opcd_ext>
<syntax><mnem>SBB</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
<entry op_size="0" lock="yes">
<opcd_ext>4</opcd_ext>
<syntax><mnem>AND</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
<entry op_size="0" lock="yes">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SUB</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
<entry op_size="0" lock="yes">
<opcd_ext>6</opcd_ext>
<syntax><mnem>XOR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>7</opcd_ext>
<syntax><mnem>CMP</mnem><src><a>E</a><t>b</t></src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="81">
<entry op_size="1" lock="yes">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ADD</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
<entry op_size="1" lock="yes">
<opcd_ext>1</opcd_ext>
<syntax><mnem>OR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
<entry op_size="1" lock="yes">
<opcd_ext>2</opcd_ext>
<syntax><mnem>ADC</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
<entry op_size="1" lock="yes">
<opcd_ext>3</opcd_ext>
<syntax><mnem>SBB</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
<entry op_size="1" lock="yes">
<opcd_ext>4</opcd_ext>
<syntax><mnem>AND</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
<entry op_size="1" lock="yes">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SUB</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
<entry op_size="1" lock="yes">
<opcd_ext>6</opcd_ext>
<syntax><mnem>XOR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>7</opcd_ext>
<syntax><mnem>CMP</mnem><src><a>E</a><t>vqp</t></src><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="82">
<entry op_size="0" alias="80_0" lock="yes">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ADD</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
<entry op_size="0" alias="80_1" lock="yes">
<opcd_ext>1</opcd_ext>
<syntax><mnem>OR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
<entry op_size="0" alias="80_2" lock="yes">
<opcd_ext>2</opcd_ext>
<syntax><mnem>ADC</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
<entry op_size="0" alias="80_3" lock="yes">
<opcd_ext>3</opcd_ext>
<syntax><mnem>SBB</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
<entry op_size="0" alias="80_4" lock="yes">
<opcd_ext>4</opcd_ext>
<syntax><mnem>AND</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
<entry op_size="0" alias="80_5" lock="yes">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SUB</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
<entry op_size="0" alias="80_6" lock="yes">
<opcd_ext>6</opcd_ext>
<syntax><mnem>XOR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
<entry op_size="0" alias="80_7">
<opcd_ext>7</opcd_ext>
<syntax><mnem>CMP</mnem><src><a>E</a><t>b</t></src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="83">
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ADD</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add</brief></note>
</entry>
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>1</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>OR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Inclusive OR</brief></note>
</entry>
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>2</opcd_ext>
<syntax><mnem>ADC</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Add with Carry</brief></note>
</entry>
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>3</opcd_ext>
<syntax><mnem>SBB</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Integer Subtraction with Borrow</brief></note>
</entry>
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>4</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>AND</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical AND</brief></note>
</entry>
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SUB</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Subtract</brief></note>
</entry>
<entry sign-ext="1" op_size="1" lock="yes">
<opcd_ext>6</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>XOR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
<entry sign-ext="1" op_size="1">
<opcd_ext>7</opcd_ext>
<syntax><mnem>CMP</mnem><src><a>E</a><t>vqp</t></src><src><a>I</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare Two Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="84">
<entry direction="0" op_size="0" r="yes">
<syntax><mnem>TEST</mnem><src><a>E</a><t>b</t></src><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="85">
<entry direction="0" op_size="1" r="yes">
<syntax><mnem>TEST</mnem><src><a>E</a><t>vqp</t></src><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="86">
<entry direction="1" op_size="0" r="yes" lock="yes">
<syntax><mnem>XCHG</mnem><dst><a>G</a><t>b</t></dst><dst><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Exchange Register/Memory with Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="87">
<entry direction="1" op_size="1" r="yes" lock="yes">
<syntax><mnem>XCHG</mnem><dst><a>G</a><t>vqp</t></dst><dst><a>E</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Exchange Register/Memory with Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="88">
<entry direction="0" op_size="0" r="yes">
<syntax><mnem>MOV</mnem><dst depend="no"><a>E</a><t>b</t></dst><src><a>G</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="89">
<entry direction="0" op_size="1" r="yes">
<syntax><mnem>MOV</mnem><dst depend="no"><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8A">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>MOV</mnem><dst depend="no"><a>G</a><t>b</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8B">
<entry direction="1" op_size="0" r="yes">
<syntax><mnem>MOV</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8C">
<entry direction="0" r="yes">
<syntax mod="mem">
<mnem>MOV</mnem>
<dst depend="no"><a>M</a><t>w</t></dst>
<src><a>S</a><t>w</t></src>
</syntax>
<syntax mod="nomem">
<mnem>MOV</mnem>
<dst depend="no"><a>R</a><t>vqp</t></dst>
<src><a>S</a><t>w</t></src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8D">
<entry r="yes">
<syntax><mnem>LEA</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src depend="no"><a>M</a></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Load Effective Address</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8E">
<entry direction="1" r="yes">
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>S</a><t>w</t></dst>
<src><a>E</a><t>w</t></src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8F">
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>POP</mnem>
<dst depend="no"><a>E</a><t>v</t></dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
<entry op_size="1" mode="e">
<opcd_ext>0</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>POP</mnem>
<dst depend="no"><a>E</a><t>vq</t></dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="90">
<entry attr="acc">
<syntax>
<mnem>XCHG</mnem>
<dst><a>Z</a><t>vqp</t></dst>
<dst nr="0" group="gen" type="vqp">rAX</dst>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Exchange Register/Memory with Register</brief></note>
</entry>
<entry doc_ref="gen_note_90_NOP">
<syntax>
<mnem>NOP</mnem>
</syntax>
<grp1>gen</grp1><grp2>control</grp2>
<note><brief>No Operation</brief></note>
</entry>
<entry attr="nop" doc_ref="gen_note_plain_F390" particular="yes">
<pref>F3</pref>
<proc_end>09</proc_end>
<!-- 1.02 <syntax/>-->
<syntax>
<mnem>NOP</mnem>
</syntax>
<grp1>gen</grp1><grp2>control</grp2>
<note><brief>No Operation</brief></note>
</entry>
<entry>
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax><mnem>PAUSE</mnem></syntax>
<instr_ext>sse2</instr_ext>
<grp1>cachect</grp1>
<note><brief>Spin Loop Hint</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="98">
<entry>
<syntax>
<mnem>CBW</mnem>
<!--<dst nr="4" group="gen" type="b" displayed="no" depend="no">AH</dst> changed to AX in 1.02-->
<dst nr="0" group="gen" type="wo" displayed="no">AX</dst>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Convert Byte to Word</brief></note>
</entry>
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>CWDE</mnem>
<!--<dst nr="0" group="gen" type="d" displayed="no">EAX</dst> 1.02-->
<dst nr="0" group="gen" type="do" displayed="no">EAX</dst>
<src nr="0" group="gen" type="w" displayed="no">AX</src>
<!-- no "wo" type because this syntax is applied if current operand size is 32 bits -->
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Convert Word to Doubleword</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>CBW</mnem> <!-- duplicated -->
<!--<dst nr="4" group="gen" type="b" displayed="no" depend="no">AH</dst> changed to AX in 1.02-->
<dst nr="0" group="gen" type="wo" displayed="no">AX</dst>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
</syntax>
<syntax>
<mnem>CWDE</mnem> <!-- duplicated -->
<!--<dst nr="0" group="gen" type="d" displayed="no">EAX</dst> 1.02-->
<dst nr="0" group="gen" type="do" displayed="no">EAX</dst>
<src nr="0" group="gen" type="w" displayed="no">AX</src>
<!-- no "wo" type because this syntax is applied if current operand size is 32 bits -->
</syntax>
<syntax>
<mnem>CDQE</mnem>
<dst nr="0" group="gen" type="qp" displayed="no">RAX</dst>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
<!-- no "do" type because this syntax is applied if current operand size is 64 bits -->
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Convert</brief></note>
</entry>
</pri_opcd>
<!-- 99 -->
<pri_opcd value="99">
<entry>
<syntax>
<mnem>CWD</mnem>
<!--<dst nr="2" group="gen" type="w" displayed="no" depend="no">DX</dst> 1.02 -->
<dst nr="2" group="gen" type="wo" displayed="no" depend="no">DX</dst>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Convert Word to Doubleword</brief></note>
</entry>
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>CDQ</mnem>
<!--<dst nr="2" group="gen" type="d" displayed="no" depend="no">EDX</dst> 1.02-->
<dst nr="2" group="gen" type="do" displayed="no" depend="no">EDX</dst>
<!--<src nr="0" group="gen" type="d" displayed="no">EAX</src> 1.02-->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Convert Doubleword to Quadword</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>CWD</mnem> <!-- duplicated -->
<!--<dst nr="2" group="gen" type="w" displayed="no" depend="no">DX</dst> 1.02-->
<dst nr="2" group="gen" type="wo" displayed="no" depend="no">DX</dst>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<syntax>
<mnem>CDQ</mnem> <!-- duplicated -->
<!--<dst nr="2" group="gen" type="d" displayed="no" depend="no">EDX</dst> 1.02-->
<dst nr="2" group="gen" type="do" displayed="no" depend="no">EDX</dst>
<!--<src nr="0" group="gen" type="d" displayed="no">EAX</src> 1.02-->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
</syntax>
<syntax>
<mnem>CQO</mnem>
<dst nr="2" group="gen" type="qp" displayed="no">RDX</dst>
<src nr="0" group="gen" type="qp" displayed="no">RAX</src>
</syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Convert</brief></note>
</entry>
</pri_opcd>
<!-- 9A -->
<pri_opcd value="9A">
<entry>
<syntax>
<mnem>CALLF</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>A</a><t>p</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<!-- 9B --> <!-- both instruction and prefix -->
<pri_opcd value="9B">
<entry>
<syntax><mnem>FWAIT</mnem></syntax>
<syntax><mnem>WAIT</mnem></syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Check pending unmasked floating-point exceptions</brief></note>
</entry>
<entry>
<syntax/>
<grp1>prefix</grp1><grp2>x87fpu</grp2><grp3>control</grp3>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Wait Prefix</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9C">
<entry>
<syntax>
<mnem>PUSHF</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="wo" address="F" displayed="no">Flags</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>flgctrl</grp2>
<!-- 1.10 <test_f>odiszapc</test_f>-->
<note><brief>Push FLAGS Register onto the Stack</brief></note>
</entry>
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>PUSHFD</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="do" address="F" displayed="no">EFlags</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>flgctrl</grp2>
<!-- 1.10 <test_f>odiszapc</test_f>-->
<note><brief>Push eFLAGS Register onto the Stack</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>PUSHF</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="ws" address="F" displayed="no">Flags</src>
</syntax>
<syntax>
<mnem>PUSHFQ</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="qs" address="F" displayed="no">RFlags</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>flgctrl</grp2>
<!-- 1.10 <test_f>odiszapc</test_f>-->
<note><brief>Push rFLAGS Register onto the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9D">
<entry>
<syntax>
<mnem>POPF</mnem>
<dst type="wo" address="F" displayed="no" depend="no">Flags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>flgctrl</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Pop Stack into FLAGS Register</brief></note>
</entry>
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>POPFD</mnem>
<dst type="do" address="F" displayed="no" depend="no">EFlags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>flgctrl</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Pop Stack into eFLAGS Register</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>POPF</mnem>
<dst type="ws" address="F" displayed="no" depend="no">Flags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<syntax>
<mnem>POPFQ</mnem>
<dst type="qs" address="F" displayed="no" depend="no">RFlags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>flgctrl</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Pop Stack into rFLAGS Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9E">
<entry doc64_ref="gen_note_SAHF_9E_LAHF_9F">
<syntax>
<mnem>SAHF</mnem>
<src nr="4" group="gen" type="b" displayed="no">AH</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>flgctrl</grp2>
<modif_f>szapc</modif_f><def_f>szapc</def_f>
<note><brief>Store AH into Flags</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9F">
<entry doc64_ref="gen_note_SAHF_9E_LAHF_9F">
<syntax>
<mnem>LAHF</mnem>
<dst nr="4" group="gen" type="b" displayed="no" depend="no">AH</dst>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>flgctrl</grp2>
<test_f>szapc</test_f>
<note><brief>Load Status Flags into AH Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A0">
<entry op_size="0">
<syntax>
<mnem>MOV</mnem>
<dst nr="0" group="gen" type="b" depend="no">AL</dst>
<src><a>O</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A1">
<entry op_size="1">
<syntax>
<mnem>MOV</mnem>
<dst nr="0" group="gen" type="vqp" depend="no">rAX</dst>
<src><a>O</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A2">
<entry op_size="0">
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>O</a><t>b</t></dst>
<src nr="0" group="gen" type="b">AL</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A3">
<entry op_size="1">
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>O</a><t>vqp</t></dst>
<src nr="0" group="gen" type="vqp">rAX</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A4">
<entry op_size="0">
<syntax>
<mnem>MOVS</mnem>
<!--<dst depend="no"><a>Y</a><t>b</t></dst> 1.02-->
<dst type="b" address="Y" depend="no">(ES:)[rDI]</dst>
<!--<src><a>X</a><t>b</t></src> 1.02-->
<src type="b" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>MOVSB</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>b</t></dst> 1.02-->
<dst type="b" address="Y" displayed="no" depend="no">(ES:)[rDI]</dst>
<!--<src displayed="no"><a>X</a><t>b</t></src> 1.02-->
<src type="b" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Move Data from String to String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A5">
<entry op_size="1">
<syntax>
<mnem>MOVS</mnem>
<!--<dst depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" depend="no">ES:[DI]</dst>
<!--<src><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X">DS:[SI]</src>
</syntax>
<syntax>
<mnem>MOVSW</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" displayed="no" depend="no">ES:[DI]</dst>
<!--<src displayed="no"><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X" displayed="no">DS:[SI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Move Data from String to String</brief></note>
</entry>
<entry op_size="1">
<proc_start>03</proc_start>
<syntax>
<mnem>MOVS</mnem>
<!--<dst depend="no"><a>Y</a><t>v</t></dst> 1.02-->
<dst type="v" address="Y" depend="no">(ES:)[rDI]</dst>
<!--<src><a>X</a><t>v</t></src> 1.02-->
<src type="v" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>MOVSD</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>d</t></dst> 1.02-->
<dst type="do" address="Y" displayed="no" depend="no">(ES:)[rDI]</dst>
<!--<src displayed="no"><a>X</a><t>d</t></src> 1.02-->
<src type="do" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Move Data from String to String</brief></note>
</entry>
<entry op_size="1" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>MOVS</mnem>
<!--<dst depend="no"><a>Y</a><t>vqp</t></dst> 1.02-->
<dst type="vqp" address="Y" depend="no">[rDI]</dst>
<!--<src><a>X</a><t>vqp</t></src> 1.02-->
<src type="vqp" address="X">[rSI]</src>
</syntax>
<syntax>
<mnem>MOVSW</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" displayed="no" depend="no">[rDI]</dst>
<!--<src displayed="no"><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X" displayed="no">[rSI]</src>
</syntax>
<syntax>
<mnem>MOVSD</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>d</t></dst> 1.02-->
<dst type="do" address="Y" displayed="no" depend="no">[rDI]</dst>
<!--<src displayed="no"><a>X</a><t>d</t></src> 1.02-->
<src type="do" address="X" displayed="no">[rSI]</src>
</syntax>
<syntax>
<mnem>MOVSQ</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>qp</t></dst> 1.02-->
<dst type="qp" address="Y" displayed="no" depend="no">[rDI]</dst>
<!--<src displayed="no"><a>X</a><t>qp</t></src> 1.02-->
<src type="qp" address="X" displayed="no">[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Move Data from String to String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A6">
<entry op_size="0">
<syntax>
<mnem>CMPS</mnem>
<!--<src><a>Y</a><t>b</t></src> 1.02-->
<src type="b" address="Y">(ES:)[rDI]</src>
<!--<src><a>X</a><t>b</t></src> 1.02-->
<src type="b" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>CMPSB</mnem>
<!--<src displayed="no"><a>Y</a><t>b</t></src> 1.02-->
<src type="b" address="Y" displayed="no">(ES:)[rDI]</src>
<!--<src displayed="no"><a>X</a><t>b</t></src> 1.02-->
<src type="b" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare String Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A7">
<entry op_size="1">
<syntax>
<mnem>CMPS</mnem>
<!--<src><a>Y</a><t>w</t></src> 1.02-->
<src type="wo" address="Y">ES:[DI]</src>
<!--<src><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X">DS:[SI]</src>
</syntax>
<syntax>
<mnem>CMPSW</mnem>
<!--<src displayed="no"><a>Y</a><t>w</t></src> 1.02-->
<src type="wo" address="Y" displayed="no">ES:[DI]</src>
<!--<src displayed="no"><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X" displayed="no">DS:[SI]</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare String Operands</brief></note>
</entry>
<entry op_size="1">
<proc_start>03</proc_start>
<syntax>
<mnem>CMPS</mnem>
<!--<src><a>Y</a><t>v</t></src> 1.02-->
<src type="v" address="Y">(ES:)[rDI]</src>
<!--<src><a>X</a><t>v</t></src> 1.02-->
<src type="v" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>CMPSD</mnem>
<!--<src displayed="no"><a>Y</a><t>d</t></src> 1.02-->
<src type="do" address="Y" displayed="no">(ES:)[rDI]</src>
<!--<src displayed="no"><a>X</a><t>d</t></src> 1.02-->
<src type="do" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare String Operands</brief></note>
</entry>
<entry op_size="1" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>CMPS</mnem>
<!--<src><a>Y</a><t>vqp</t></src> 1.02-->
<src type="vqp" address="Y">[rDI]</src>
<!--<src><a>X</a><t>vqp</t></src> 1.02-->
<src type="vqp" address="X">[rSI]</src>
</syntax>
<syntax>
<mnem>CMPSW</mnem>
<!--<src displayed="no"><a>Y</a><t>w</t></src> 1.02-->
<src type="wo" address="Y" displayed="no">[rDI]</src>
<!--<src displayed="no"><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X" displayed="no">[rSI]</src>
</syntax>
<syntax>
<mnem>CMPSD</mnem>
<!--<src displayed="no"><a>Y</a><t>d</t></src> 1.02-->
<src type="do" address="Y" displayed="no">[rDI]</src>
<!--<src displayed="no"><a>X</a><t>d</t></src> 1.02-->
<src type="do" address="X" displayed="no">[rSI]</src>
</syntax>
<syntax>
<mnem>CMPSQ</mnem>
<!--<src displayed="no"><a>Y</a><t>qp</t></src> 1.02-->
<src type="qp" address="Y" displayed="no">[rDI]</src>
<!--<src displayed="no"><a>X</a><t>qp</t></src> 1.02-->
<src type="qp" address="X" displayed="no">[rSI]</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare String Operands</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A8">
<entry op_size="0" attr="acc">
<syntax><mnem>TEST</mnem><src nr="0" group="gen" type="b">AL</src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A9">
<entry op_size="1" attr="acc">
<syntax><mnem>TEST</mnem><src nr="0" group="gen" type="vqp">rAX</src><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AA">
<entry op_size="0">
<syntax>
<mnem>STOS</mnem>
<!--<dst depend="no"><a>Y</a><t>b</t></dst> 1.02-->
<dst type="b" address="Y" depend="no">(ES:)[rDI]</dst>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
</syntax>
<syntax>
<mnem>STOSB</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>b</t></dst> 1.02-->
<dst type="b" address="Y" displayed="no" depend="no">(ES:)[rDI]</dst>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Store String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AB">
<entry op_size="1">
<syntax>
<mnem>STOS</mnem>
<!--<dst depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" depend="no">ES:[DI]</dst>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<syntax>
<mnem>STOSW</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" displayed="no" depend="no">ES:[DI]</dst>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Store String</brief></note>
</entry>
<entry op_size="1">
<proc_start>03</proc_start>
<syntax>
<mnem>STOS</mnem>
<!--<dst depend="no"><a>Y</a><t>v</t></dst> 1.02-->
<dst type="v" address="Y" depend="no">(ES:)[rDI]</dst>
<src nr="0" group="gen" type="v" displayed="no">eAX</src>
</syntax>
<syntax>
<mnem>STOSD</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>d</t></dst> 1.02-->
<dst type="do" address="Y" displayed="no" depend="no">(ES:)[rDI]</dst>
<!--<src nr="0" group="gen" type="d" displayed="no">EAX</src> 1.02-->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Store String</brief></note>
</entry>
<entry op_size="1" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>STOS</mnem>
<!--<dst depend="no"><a>Y</a><t>vqp</t></dst> 1.02-->
<dst type="vqp" address="Y" depend="no">[rDI]</dst>
<src nr="0" group="gen" type="vqp" displayed="no">rAX</src>
</syntax>
<syntax>
<mnem>STOSW</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>w</t></dst> 1.02-->
<dst type="wo" address="Y" displayed="no" depend="no">[rDI]</dst>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<syntax>
<mnem>STOSD</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>d</t></dst> 1.02-->
<dst type="do" address="Y" displayed="no" depend="no">[rDI]</dst>
<!--<src nr="0" group="gen" type="d" displayed="no">EAX</src> 1.02-->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
</syntax>
<syntax>
<mnem>STOSQ</mnem>
<!--<dst displayed="no" depend="no"><a>Y</a><t>qp</t></dst> 1.02-->
<dst type="qp" address="Y" displayed="no" depend="no">[rDI]</dst>
<src nr="0" group="gen" type="qp" displayed="no">RAX</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Store String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AC">
<entry op_size="0">
<syntax>
<mnem>LODS</mnem>
<dst nr="0" group="gen" type="b" depend="no" displayed="no">AL</dst>
<!--<src><a>X</a><t>b</t></src> 1.02-->
<src type="b" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>LODSB</mnem>
<dst nr="0" group="gen" type="b" depend="no" displayed="no">AL</dst>
<!--<src displayed="no"><a>X</a><t>b</t></src> 1.02-->
<src type="b" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Load String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AD">
<entry op_size="1">
<syntax>
<mnem>LODS</mnem>
<!--<dst nr="0" group="gen" type="w" displayed="no">AX</dst> 1.02-->
<dst nr="0" group="gen" type="wo" depend="no" displayed="no">AX</dst>
<!--<src><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X">DS:[SI]</src>
</syntax>
<syntax>
<mnem>LODSW</mnem>
<!--<dst nr="0" group="gen" type="w" displayed="no">AX</dst> 1.02-->
<dst nr="0" group="gen" type="wo" depend="no" displayed="no">AX</dst>
<!--<src displayed="no"><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X" displayed="no">DS:[SI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Load String</brief></note>
</entry>
<entry op_size="1">
<proc_start>03</proc_start>
<syntax>
<mnem>LODS</mnem>
<dst nr="0" group="gen" type="v" depend="no" displayed="no">eAX</dst>
<!--<src><a>X</a><t>v</t></src> 1.02-->
<src type="v" address="X">(DS:)[rSI]</src>
</syntax>
<syntax>
<mnem>LODSD</mnem>
<!--<dst nr="0" group="gen" type="d" displayed="no">EAX</dst> 1.02-->
<dst nr="0" group="gen" type="do" depend="no" displayed="no">EAX</dst>
<!--<src displayed="no"><a>X</a><t>d</t></src>-->
<src type="do" address="X" displayed="no">(DS:)[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Load String</brief></note>
</entry>
<entry op_size="1" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>LODS</mnem>
<dst nr="0" group="gen" type="vqp" depend="no" displayed="no">rAX</dst>
<!--<src><a>X</a><t>vqp</t></src> 1.02-->
<src type="vqp" address="X">[rSI]</src>
</syntax>
<syntax>
<mnem>LODSW</mnem>
<!--<dst nr="0" group="gen" type="w" displayed="no">AX</dst> 1.02-->
<dst nr="0" group="gen" type="wo" depend="no" displayed="no">AX</dst>
<!--<src displayed="no"><a>X</a><t>w</t></src> 1.02-->
<src type="wo" address="X" displayed="no">[rSI]</src>
</syntax>
<syntax>
<mnem>LODSD</mnem>
<!--<dst nr="0" group="gen" type="d" displayed="no">EAX</dst> 1.02-->
<dst nr="0" group="gen" type="do" depend="no" displayed="no">EAX</dst>
<!--<src displayed="no"><a>X</a><t>d</t></src> 1.02-->
<src type="do" address="X" displayed="no">[rSI]</src>
</syntax>
<syntax>
<mnem>LODSQ</mnem>
<dst nr="0" group="gen" type="qp" depend="no" displayed="no">RAX</dst>
<!--<src displayed="no"><a>X</a><t>qp</t></src> 1.02-->
<src type="qp" address="X" displayed="no">[rSI]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2><grp2>string</grp2>
<test_f>d</test_f>
<note><brief>Load String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AE">
<entry op_size="0">
<syntax>
<mnem>SCAS</mnem>
<!--<src><a>Y</a><t>b</t></src> 1.02-->
<src type="b" address="Y">(ES:)[rDI]</src>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
</syntax>
<syntax>
<mnem>SCASB</mnem>
<!--<src displayed="no"><a>Y</a><t>b</t></src> 1.02-->
<src type="b" address="Y" displayed="no">(ES:)[rDI]</src>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Scan String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AF">
<entry op_size="1">
<syntax>
<mnem>SCAS</mnem>
<!--<src><a>Y</a><t>w</t></src> 1.02-->
<src type="wo" address="Y">ES:[DI]</src>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<syntax>
<mnem>SCASW</mnem>
<!--<src displayed="no"><a>Y</a><t>w</t></src> 1.02-->
<src type="wo" address="Y" displayed="no">ES:[DI]</src>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Scan String</brief></note>
</entry>
<entry op_size="1">
<proc_start>03</proc_start>
<syntax>
<mnem>SCAS</mnem>
<!--<src><a>Y</a><t>v</t></src> 1.02-->
<src type="v" address="Y">(ES:)[rDI]</src>
<src nr="0" group="gen" type="v" displayed="no">eAX</src>
</syntax>
<syntax>
<mnem>SCASD</mnem>
<!--<src displayed="no"><a>Y</a><t>d</t></src> 1.02-->
<src type="do" address="Y" displayed="no">(ES:)[rDI]</src>
<!--<src nr="0" group="gen" type="d" displayed="no">EAX</src> 1.02-->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Scan String</brief></note>
</entry>
<entry op_size="1" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>SCAS</mnem>
<!--<src><a>Y</a><t>vqp</t></src> 1.02-->
<src type="vqp" address="Y">[rDI]</src>
<src nr="0" group="gen" type="vqp" displayed="no">rAX</src>
</syntax>
<syntax>
<mnem>SCASW</mnem>
<!--<src displayed="no"><a>Y</a><t>w</t></src> 1.02-->
<src type="wo" address="Y" displayed="no">[rDI]</src>
<!--<src nr="0" group="gen" type="w" displayed="no">AX</src> 1.02-->
<src nr="0" group="gen" type="wo" displayed="no">AX</src>
</syntax>
<syntax>
<mnem>SCASD</mnem>
<!--<src displayed="no"><a>Y</a><t>d</t></src> 1.02-->
<src type="do" address="Y" displayed="no">[rDI]</src>
<!--<src nr="0" group="gen" type="v" displayed="no">EAX</src> 1.02--> <!-- "v" fixed to "do" -->
<src nr="0" group="gen" type="do" displayed="no">EAX</src>
</syntax>
<syntax>
<mnem>SCASQ</mnem>
<!--<src displayed="no"><a>Y</a><t>qp</t></src> 1.02-->
<src type="qp" address="Y" displayed="no">[rDI]</src>
<src nr="0" group="gen" type="qp" displayed="no">RAX</src>
</syntax>
<grp1>gen</grp1>
<grp2>arith</grp2><grp2>string</grp2>
<grp3>binary</grp3>
<test_f>d</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Scan String</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B0">
<entry>
<syntax><mnem>MOV</mnem><dst depend="no"><a>Z</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B8">
<entry>
<syntax><mnem>MOV</mnem><dst depend="no"><a>Z</a><t>vqp</t></dst><src><a>I</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C0">
<proc_start>01</proc_start>
<entry op_size="0">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ROL</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>1</opcd_ext>
<syntax><mnem>ROR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>2</opcd_ext>
<syntax><mnem>RCL</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>3</opcd_ext>
<syntax><mnem>RCR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>4</opcd_ext>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SHR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0" alias="C0_4" doc="u" doc_ref="gen_note_SAL_C0_4_C1_4_D0_4_D1_4">
<opcd_ext>6</opcd_ext>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>7</opcd_ext>
<syntax><mnem>SAR</mnem><dst><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oa</undef_f>
<note><brief>Shift</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C1">
<proc_start>01</proc_start>
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ROL</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>1</opcd_ext>
<syntax><mnem>ROR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>2</opcd_ext>
<syntax><mnem>RCL</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>3</opcd_ext>
<syntax><mnem>RCR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>4</opcd_ext>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SHR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0" alias="C1_4" doc="u" doc_ref="gen_note_SAL_C0_4_C1_4_D0_4_D1_4">
<opcd_ext>6</opcd_ext>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>7</opcd_ext>
<syntax><mnem>SAR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oa</undef_f>
<note><brief>Shift</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C2">
<entry>
<syntax>
<mnem>RETN</mnem>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
<src><a>I</a><t>w</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Return from procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C3">
<entry>
<syntax>
<mnem>RETN</mnem>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Return from procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C4">
<!--<entry r="yes" mod="mem">-->
<entry r="yes">
<syntax>
<mnem>LES</mnem>
<dst nr="0" group="seg" type="w" displayed="no">ES</dst>
<dst depend="no"><a>G</a><t>v</t></dst>
<src><a>M</a><t>p</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>segreg</grp2>
<note><brief>Load Far Pointer</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C5">
<!--<entry r="yes" mod="mem">-->
<entry r="yes">
<syntax>
<mnem>LDS</mnem>
<dst nr="3" group="seg" type="w" displayed="no">DS</dst>
<dst depend="no"><a>G</a><t>v</t></dst>
<src><a>M</a><t>p</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>segreg</grp2>
<note><brief>Load Far Pointer</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C6">
<entry op_size="0">
<opcd_ext>0</opcd_ext>
<syntax><mnem>MOV</mnem><dst depend="no"><a>E</a><t>b</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C7">
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax><mnem>MOV</mnem><dst depend="no"><a>E</a><t>vqp</t></dst><src><a>I</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Move</brief></note>
</entry>
</pri_opcd>
<!-- 1.02
<pri_opcd value="C8">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>ENTER</mnem>
<dst nr="5" group="gen" type="vs" displayed="no">rBP</dst>
<src><a>I</a><t>w</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Make Stack Frame for Procedure Parameters</brief></note>
</entry>
</pri_opcd>
-->
<pri_opcd value="C8">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>ENTER</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<dst nr="5" group="gen" type="v" displayed="no">eBP</dst>
<src><a>I</a><t>w</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Make Stack Frame for Procedure Parameters</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>ENTER</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<dst nr="5" group="gen" type="vq" displayed="no">rBP</dst>
<src><a>I</a><t>w</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Make Stack Frame for Procedure Parameters</brief></note>
</entry>
</pri_opcd>
<!-- 1.02
<pri_opcd value="C9">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>LEAVE</mnem>
<dst nr="5" group="gen" type="vs" displayed="no">rBP</dst>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>High Level Procedure Exit</brief></note>
</entry>
</pri_opcd>
-->
<pri_opcd value="C9">
<entry>
<proc_start>01</proc_start>
<syntax>
<mnem>LEAVE</mnem>
<dst nr="5" group="gen" type="v" displayed="no">eBP</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>High Level Procedure Exit</brief></note>
</entry>
<entry mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>LEAVE</mnem>
<dst nr="5" group="gen" type="vq" displayed="no">rBP</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>High Level Procedure Exit</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="CA">
<entry ring="f">
<syntax>
<mnem>RETF</mnem>
<src><a>I</a><t>w</t></src>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Return from procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="CB">
<entry ring="f">
<syntax>
<mnem>RETF</mnem>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Return from procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="CC">
<entry alias="CD" ring="f">
<syntax>
<mnem>INT</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src address="I">3</src>
<src type="v" address="F" displayed="no">eFlags</src>
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<!-- <test_f>odiszapc</test_f>-->
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Call to Interrupt Procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="CD">
<entry ring="f">
<syntax>
<mnem>INT</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>I</a><t>b</t></src>
<src type="v" address="F" displayed="no">eFlags</src>
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<!-- <test_f>odiszapc</test_f>-->
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Call to Interrupt Procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="CE">
<entry ring="f">
<syntax>
<mnem>INTO</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="v" address="F" displayed="no">eFlags</src>
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<test_f>o</test_f>
<modif_f cond="yes">i</modif_f>
<def_f cond="yes">i</def_f>
<f_vals>i</f_vals>
<note><brief>Call to Interrupt Procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="CF">
<entry ring="f">
<syntax>
<mnem>IRET</mnem>
<dst type="wo" address="F" displayed="no">Flags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Interrupt Return</brief></note>
</entry>
<entry ring="f">
<proc_start>03</proc_start>
<syntax>
<mnem>IRETD</mnem>
<dst type="do" address="F" displayed="no">EFlags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Interrupt Return</brief></note>
</entry>
<entry ring="f" mode="e">
<syntax> <!-- duplicated -->
<mnem>IRET</mnem>
<dst type="wo" address="F" displayed="no">Flags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<syntax> <!-- duplicated -->
<mnem>IRETD</mnem>
<dst type="do" address="F" displayed="no">EFlags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<syntax>
<mnem>IRETQ</mnem>
<dst type="qp" address="F" displayed="no">RFlags</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Interrupt Return</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D0">
<entry op_size="0">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ROL</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>1</opcd_ext>
<syntax><mnem>ROR</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>2</opcd_ext>
<syntax><mnem>RCL</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>3</opcd_ext>
<syntax><mnem>RCR</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>4</opcd_ext>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SHR</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0" alias="D0_4" doc="u" doc_ref="gen_note_SAL_C0_4_C1_4_D0_4_D1_4">
<opcd_ext>6</opcd_ext>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>7</opcd_ext>
<syntax><mnem>SAR</mnem><dst><a>E</a><t>b</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D1">
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ROL</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>1</opcd_ext>
<syntax><mnem>ROR</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>2</opcd_ext>
<syntax><mnem>RCL</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>3</opcd_ext>
<syntax><mnem>RCR</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>4</opcd_ext>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SHR</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1" alias="D1_4" doc="u" doc_ref="gen_note_SAL_C0_4_C1_4_D0_4_D1_4">
<opcd_ext>6</opcd_ext>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>7</opcd_ext>
<syntax><mnem>SAR</mnem><dst><a>E</a><t>vqp</t></dst><src address="I">1</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D2">
<entry op_size="0">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ROL</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>1</opcd_ext>
<syntax><mnem>ROR</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>2</opcd_ext>
<syntax><mnem>RCL</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>3</opcd_ext>
<syntax><mnem>RCR</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>4</opcd_ext>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SHR</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0" alias="D2_4" doc="u" doc_ref="gen_note_SAL_C0_4_C1_4_D0_4_D1_4">
<opcd_ext>6</opcd_ext>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>7</opcd_ext>
<syntax><mnem>SAR</mnem><dst><a>E</a><t>b</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oa</undef_f>
<note><brief>Shift</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D3">
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax><mnem>ROL</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>1</opcd_ext>
<syntax><mnem>ROR</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>2</opcd_ext>
<syntax><mnem>RCL</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>3</opcd_ext>
<syntax><mnem>RCR</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<test_f>c</test_f><modif_f>oszapc</modif_f><def_f>oszapc</def_f><undef_f>o</undef_f>
<note><brief>Rotate</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>4</opcd_ext>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>5</opcd_ext>
<syntax><mnem>SHR</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1" alias="D3_4" doc="u" doc_ref="gen_note_SAL_C0_4_C1_4_D0_4_D1_4">
<opcd_ext>6</opcd_ext>
<syntax><mnem>SAL</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<syntax><mnem>SHL</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Shift</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>7</opcd_ext>
<syntax><mnem>SAR</mnem><dst><a>E</a><t>vqp</t></dst><src nr="1" group="gen" type="b">CL</src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f>
<note><brief>Shift</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D4">
<entry>
<sec_opcd>0A</sec_opcd>
<syntax>
<mnem>AAM</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no" depend="no">AH</dst>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<modif_f>oszapc</modif_f><def_f>szp</def_f><undef_f>oac</undef_f>
<note><brief>ASCII Adjust AX After Multiply</brief></note>
</entry>
<entry>
<syntax>
<mnem sug="yes">AMX</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no" depend="no">AH</dst>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<modif_f>oszapc</modif_f><def_f>szp</def_f><undef_f>oac</undef_f>
<note><brief>Adjust AX After Multiply</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D5">
<entry>
<sec_opcd>0A</sec_opcd>
<syntax>
<mnem>AAD</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no">AH</dst>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<modif_f>oszapc</modif_f><def_f>szp</def_f><undef_f>oac</undef_f>
<note><brief>ASCII Adjust AX Before Division</brief></note>
</entry>
<entry>
<syntax>
<mnem sug="yes">ADX</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no">AH</dst>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>decimal</grp3>
<modif_f>oszapc</modif_f><def_f>szp</def_f><undef_f>oac</undef_f>
<note><brief>Adjust AX Before Division</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D6">
<entry attr="undef" is_undoc="yes"
doc_ref="gen_note_undefined_D6_F1" particular="yes">
<proc_start>02</proc_start>
<syntax/>
<note><brief>Undefined and Reserved; Does not Generate #UD</brief></note>
</entry>
<entry doc="u" is_doc="yes" doc_ref="gen_note_u_SALC_D6">
<proc_start>02</proc_start>
<syntax>
<mnem>SALC</mnem>
<dst nr="0" group="gen" type="b" displayed="no" depend="no">AL</dst>
</syntax>
<syntax>
<mnem>SETALC</mnem>
<dst nr="0" group="gen" type="b" displayed="no" depend="no">AL</dst>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<note><brief>Set AL If Carry</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D7">
<entry>
<syntax>
<mnem>XLAT</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<!--<src><a>BB</a><t>b</t></src> changed in 1.02 -->
<src type="b" address="BB">(DS:)[rBX+AL]</src>
</syntax>
<syntax>
<mnem>XLATB</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<!--<src displayed="no"><a>BB</a><t>b</t></src> changed in 1.02 -->
<src type="b" address="BB" displayed="no">(DS:)[rBX+AL]</src>
</syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Table Look-up Translation</brief></note>
</entry>
</pri_opcd>
<!-- D8 -->
<pri_opcd value="D8">
<entry mem_format="00">
<opcd_ext>0</opcd_ext>
<syntax mod="mem">
<mnem>FADD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>sr</t></src>
</syntax>
<syntax mod="nomem">
<mnem>FADD</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>1</opcd_ext>
<syntax mod="mem">
<mnem>FMUL</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>sr</t></src>
</syntax>
<syntax mod="nomem">
<mnem>FMUL</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FCOM</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src><a>ES</a><t>sr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>2</opcd_ext>
<sec_opcd>D1</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FCOM</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" address="EST" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real</brief></note>
</entry>
<entry mem_format="00" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FCOMP</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>ES</a><t>sr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>3</opcd_ext>
<sec_opcd>D9</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FCOMP</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" address="EST" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>4</opcd_ext>
<syntax mod="mem">
<mnem>FSUB</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>sr</t></src>
</syntax>
<syntax mod="nomem">
<mnem>FSUB</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>5</opcd_ext>
<syntax mod="mem">
<mnem>FSUBR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>sr</t></src>
</syntax>
<syntax mod="nomem">
<mnem>FSUBR</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>6</opcd_ext>
<syntax mod="mem">
<mnem>FDIV</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>sr</t></src>
</syntax>
<syntax mod="nomem">
<mnem>FDIV</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>7</opcd_ext>
<syntax mod="mem">
<mnem>FDIVR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>sr</t></src>
</syntax>
<syntax mod="nomem">
<mnem>FDIVR</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide</brief></note>
</entry>
</pri_opcd>
<!-- D9 -->
<pri_opcd value="D9">
<entry mem_format="00" fpush="yes">
<opcd_ext>0</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FLD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>ES</a><t>sr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Floating Point Value</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>1</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FXCH</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><dst><a>EST</a></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Exchange Register Contents</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>1</opcd_ext>
<sec_opcd>C9</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FXCH</mnem>
<dst nr="0" group="x87fpu" displayed="no">ST</dst>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Exchange Register Contents</brief></note>
</entry>
<entry mem_format="00">
<opcd_ext>2</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FST</mnem><dst><a>M</a><t>sr</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>2</opcd_ext>
<sec_opcd>D0</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FNOP</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>No Operation</brief></note>
</entry>
<entry mem_format="00" mod="mem" fpop="once">
<opcd_ext>3</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FSTP</mnem><dst><a>M</a><t>sr</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mod="nomem" part_alias="D9_3"
doc_part_alias_ref="gen_note_FSTP1_D9_3_not_true_alias"
doc_ref="gen_note_FSTP1_D9_3_FSTP8_DF_2_FSTP9_DF_3"
fpop="once" particular="yes">
<opcd_ext>3</opcd_ext>
<proc_end>02</proc_end>
<!--<syntax mod="mem">-->
<syntax>
<mnem sug="yes">FSTP1</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mod="nomem" part_alias="D9_3"
doc_part_alias_ref="gen_note_FSTP1_D9_3_not_true_alias"
doc="u" doc_ref="gen_note_x87_fpu_undoc_aliases" fpop="once"
particular="yes">
<opcd_ext>3</opcd_ext>
<proc_start>03</proc_start>
<!--<syntax mod="mem">-->
<syntax>
<mnem sug="yes">FSTP1</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry>
<opcd_ext>4</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FLDENV</mnem><src><a>M</a><t>e</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Load x87 FPU Environment</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E0</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FCHS</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Change Sign</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E1</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FABS</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Absolute Value</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E4</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FTST</mnem><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Test</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E5</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FXAM</mnem><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Examine</brief></note>
</entry>
<entry>
<opcd_ext>5</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FLDCW</mnem><src><a>M</a><t>w</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Load x87 FPU Control Word</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>E8</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLD1</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant +1.0</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>E9</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLDL2T</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant log<sub>2</sub>10</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>EA</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLDL2E</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant log<sub>2</sub>e</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>EB</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLDPI</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant &#960;</brief></note> <!-- 960 is pi code -->
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>EC</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLDLG2</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant log<sub>10</sub>2</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>ED</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLDLN2</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant log<sub>e</sub>2</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>EE</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FLDZ</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>ldconst</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Constant +0.0</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FNSTENV</mnem><dst depend="no"><a>M</a><t>e</t></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Environment</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<pref>9B</pref>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FSTENV</mnem><dst depend="no"><a>M</a><t>e</t></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Environment</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F0</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>F2XM1</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Compute 2<sup>x</sup>-1</brief></note>
</entry>
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F1</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FYL2X</mnem>
<dst nr="1" group="x87fpu" displayed="no">ST1</dst> <!-- no @address="EST"! -->
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Compute y &#215; log<sub>2</sub>x and Pop</brief></note> <!-- 215 is times code -->
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F2</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FPTAN</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>12</def_f_fpu>
<undef_f_fpu>03</undef_f_fpu>
<note><brief>Partial Tangent</brief></note>
</entry>
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F3</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FPATAN</mnem>
<dst nr="1" group="x87fpu" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Partial Arctangent and Pop</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F4</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FXTRACT</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Extract Exponent and Significand</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F5</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FPREM1</mnem>
<dst nr="0" group="x87fpu" displayed="no">ST</dst>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>IEEE Partial Remainder</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F6</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FDECSTP</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<f_vals_fpu>b</f_vals_fpu>
<note><brief>Decrement Stack-Top Pointer</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F7</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FINCSTP</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<f_vals_fpu>b</f_vals_fpu>
<note><brief>Increment Stack-Top Pointer</brief></note>
</entry>
<entry>
<opcd_ext>7</opcd_ext>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FNSTCW</mnem><dst depend="no"><a>M</a><t>w</t></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Control Word</brief></note>
</entry>
<entry>
<opcd_ext>7</opcd_ext>
<pref>9B</pref>
<!--<syntax mod="mem">-->
<syntax>
<mnem>FSTCW</mnem><dst depend="no"><a>M</a><t>w</t></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Control Word</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>F8</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FPREM</mnem>
<dst nr="0" group="x87fpu" displayed="no">ST</dst>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Partial Remainder (for compatibility with i8087 and i287)</brief></note>
</entry>
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>F9</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FYL2XP1</mnem>
<dst nr="1" group="x87fpu" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Compute y &#215; log<sub>2</sub>(x+1) and Pop</brief></note> <!-- 215 is times code -->
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>FA</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FSQRT</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Square Root</brief></note>
</entry>
<entry fpush="yes"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>FB</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FSINCOS</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>12</def_f_fpu>
<undef_f_fpu>03</undef_f_fpu>
<note><brief>Sine and Cosine</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>FC</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FRNDINT</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Round to Integer</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>FD</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FSCALE</mnem>
<dst nr="0" group="x87fpu" displayed="no">ST</dst>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Scale</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>FE</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FSIN</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>12</def_f_fpu>
<undef_f_fpu>03</undef_f_fpu>
<note><brief>Sine</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>FF</sec_opcd>
<!--<syntax mod="nomem">-->
<syntax>
<mnem>FCOS</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>trans</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>12</def_f_fpu>
<undef_f_fpu>03</undef_f_fpu>
<note><brief>Cosine</brief></note>
</entry>
</pri_opcd>
<!-- DA -->
<pri_opcd value="DA">
<entry mem_format="01" mod="mem">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FIADD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>0</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVB</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - below (CF=1)</brief></note>
</entry>
<entry mem_format="01" mod="mem">
<opcd_ext>1</opcd_ext>
<syntax>
<mnem>FIMUL</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>1</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVE</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - equal (ZF=1)</brief></note>
</entry>
<entry mem_format="01" mod="mem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FICOM</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Integer</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>2</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVBE</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - below or equal (CF=1 or ZF=1)</brief></note>
</entry>
<entry mem_format="01" mod="mem" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FICOMP</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Integer and Pop</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>3</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVU</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>p</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - unordered (PF=1)</brief></note>
</entry>
<!--<entry mem_format="01" mod="mem">-->
<entry mem_format="01">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FISUB</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract</brief></note>
</entry>
<!--<entry mem_format="01" mod="mem">-->
<entry mem_format="01">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FISUBR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract</brief></note>
</entry>
<!--<entry mod="nomem" fpop="twice">-->
<entry fpop="twice"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>E9</sec_opcd>
<proc_start>03</proc_start>
<syntax>
<mnem>FUCOMPP</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src> <!-- no @address="EST"! -->
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values and Pop Twice</brief></note>
</entry>
<!--<entry mem_format="01" mod="mem">-->
<entry mem_format="01">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FIDIV</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide</brief></note>
</entry>
<!--<entry mem_format="01" mod="mem">-->
<entry mem_format="01">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FIDIVR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide</brief></note>
</entry>
</pri_opcd>
<!-- DB -->
<pri_opcd value="DB">
<entry mem_format="01" mod="mem" fpush="yes">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FILD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>di</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Integer</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>0</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVNB</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - not below (CF=0)</brief></note>
</entry>
<entry mem_format="01" mod="mem" fpop="once">
<opcd_ext>1</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>FISTTP</mnem><dst><a>M</a><t>di</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>x87fpu</grp1>
<!-- 1.02 --> <!--<grp2>conv</grp2>-->
<grp2>conver</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<f_vals_fpu>b</f_vals_fpu>
<note><brief>Store Integer with Truncation and Pop</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>1</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVNE</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - not equal (ZF=0)</brief></note>
</entry>
<entry mem_format="01" mod="mem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FIST</mnem><dst><a>M</a><t>di</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Integer</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>2</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVNBE</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - below or equal (CF=0 and ZF=0)</brief></note>
</entry>
<entry mem_format="01" mod="mem" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FISTP</mnem><dst><a>M</a><t>di</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Integer and Pop</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>3</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCMOVNU</mnem><dst nr="0" group="x87fpu">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<test_f>p</test_f>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>FP Conditional Move - not unordered (PF=0)</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E0</sec_opcd>
<proc_start post="no">00</proc_start>
<proc_end>00</proc_end>
<syntax>
<mnem>FNENI</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<note><brief>Enable NPX Interrupt</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<pref>9B</pref>
<sec_opcd>E0</sec_opcd>
<proc_start post="no">00</proc_start>
<proc_end>00</proc_end>
<syntax>
<mnem>FENI</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<note><brief>Enable NPX Interrupt</brief></note>
</entry>
<!--<entry mod="nomem" attr="nop"
doc_ref="gen_note_FNENI_DBE0_FNDISI_DBE1" particular="yes">-->
<entry attr="nop" doc_ref="gen_note_FNENI_DBE0_FNDISI_DBE1" particular="yes">
<!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E0</sec_opcd>
<proc_start>01</proc_start>
<syntax>
<mnem>FNENI</mnem>
</syntax>
<grp1>obsol</grp1><grp2>control</grp2>
<note><brief>Treated as Integer NOP</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E1</sec_opcd>
<proc_start post="no">00</proc_start>
<proc_end>00</proc_end>
<syntax>
<mnem>FNDISI</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<note><brief>Disable NPX Interrupt</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<pref>9B</pref>
<sec_opcd>E1</sec_opcd>
<proc_start post="no">00</proc_start>
<proc_end>00</proc_end>
<syntax>
<mnem>FDISI</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<note><brief>Disable NPX Interrupt</brief></note>
</entry>
<!--<entry mod="nomem" attr="nop"
doc_ref="gen_note_FNENI_DBE0_FNDISI_DBE1" particular="yes">-->
<entry attr="nop" doc_ref="gen_note_FNENI_DBE0_FNDISI_DBE1" particular="yes">
<!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E1</sec_opcd>
<proc_start>01</proc_start>
<syntax>
<mnem>FNDISI</mnem>
</syntax>
<grp1>obsol</grp1><grp2>control</grp2>
<note><brief>Treated as Integer NOP</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E2</sec_opcd>
<syntax>
<mnem>FNCLEX</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Clear Exceptions</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<pref>9B</pref>
<sec_opcd>E2</sec_opcd>
<syntax>
<mnem>FCLEX</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Clear Exceptions</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E3</sec_opcd>
<syntax>
<mnem>FNINIT</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<f_vals_fpu>abcd</f_vals_fpu>
<note><brief>Initialize Floating-Point Unit</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<pref>9B</pref>
<sec_opcd>E3</sec_opcd>
<syntax>
<mnem>FINIT</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<f_vals_fpu>abcd</f_vals_fpu>
<note><brief>Initialize Floating-Point Unit</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E4</sec_opcd>
<proc_start post="no">02</proc_start>
<proc_end>02</proc_end>
<syntax>
<mnem>FNSETPM</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<note><brief>Set Protected Mode</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<pref>9B</pref>
<sec_opcd>E4</sec_opcd>
<proc_start post="no">02</proc_start>
<proc_end>02</proc_end>
<syntax>
<mnem>FSETPM</mnem>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<note><brief>Set Protected Mode</brief></note>
</entry>
<!--<entry mod="nomem" attr="nop" doc_ref="gen_note_FNSETPM_DBE4" particular="yes">-->
<entry attr="nop" doc_ref="gen_note_FNSETPM_DBE4" particular="yes">
<!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E4</sec_opcd>
<proc_start>03</proc_start>
<syntax>
<mnem>FNSETPM</mnem>
</syntax>
<grp1>obsol</grp1><grp2>control</grp2>
<note><brief>Treated as Integer NOP</brief></note>
</entry>
<entry mod="mem" fpush="yes">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FLD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>er</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Floating Point Value</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>5</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FUCOMI</mnem><src nr="0" group="x87fpu">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f>ozpc</modif_f>
<def_f>ozpc</def_f>
<f_vals>o</f_vals>
<modif_f_fpu>1</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values and Set EFLAGS</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry>
<opcd_ext>6</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCOMI</mnem><src nr="0" group="x87fpu">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f>ozpc</modif_f>
<def_f>ozpc</def_f>
<f_vals>o</f_vals>
<modif_f_fpu>1</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<note><brief>Compare Floating Point Values and Set EFLAGS</brief></note>
</entry>
<!--<entry mod="mem" fpop="once">-->
<entry fpop="once">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FSTP</mnem><dst><a>M</a><t>er</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
</pri_opcd>
<!-- DC -->
<pri_opcd value="DC">
<entry mem_format="10" mod="mem">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FADD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FADD</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>1</opcd_ext>
<syntax>
<mnem>FMUL</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>1</opcd_ext>
<syntax>
<mnem>FMUL</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FCOM</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real</brief></note>
</entry>
<entry mod="nomem" alias="D8_2" doc_ref="gen_note_FCOM2_DC_2"
particular="yes">
<opcd_ext>2</opcd_ext>
<proc_end>02</proc_end>
<syntax>
<mnem sug="yes">FCOM2</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real</brief></note>
</entry>
<entry mod="nomem" alias="D8_2" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" particular="yes">
<opcd_ext>2</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem sug="yes">FCOM2</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real</brief></note>
</entry>
<entry mem_format="10" mod="mem" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FCOMP</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D8_3"
doc_ref="gen_note_FCOMP3_DC_3_FCOMP5_DE_2" fpop="once"
particular="yes">
<opcd_ext>3</opcd_ext>
<proc_end>02</proc_end>
<syntax>
<mnem sug="yes">FCOMP3</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D8_3" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" fpop="once"
particular="yes">
<opcd_ext>3</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem sug="yes">FCOMP3</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FSUB</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FSUBR</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FSUBR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FSUB</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FDIV</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FDIVR</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FDIVR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FDIV</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide and Pop</brief></note>
</entry>
</pri_opcd>
<!-- DD -->
<pri_opcd value="DD">
<entry mem_format="10" mod="mem" fpush="yes">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FLD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>dr</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Floating Point Value</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FFREE</mnem><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Free Floating-Point Register</brief></note>
</entry>
<entry mod="mem" fpop="once">
<opcd_ext>1</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>FISTTP</mnem><dst><a>M</a><t>qi</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>x87fpu</grp1>
<!-- 1.02 --> <!--<grp2>conv</grp2>-->
<grp2>conver</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<f_vals_fpu>b</f_vals_fpu>
<note><brief>Store Integer with Truncation and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D9_1"
doc_ref="gen_note_FXCH4_DD_1_FXCH7_DF_1" particular="yes">
<opcd_ext>1</opcd_ext>
<proc_end>02</proc_end>
<syntax>
<mnem sug="yes">FXCH4</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><dst><a>EST</a></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Exchange Register Contents</brief></note>
</entry>
<entry mod="nomem" alias="D9_1" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" particular="yes">
<opcd_ext>1</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem sug="yes">FXCH4</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><dst><a>EST</a></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Exchange Register Contents</brief></note>
</entry>
<entry mem_format="10" mod="mem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FST</mnem><dst><a>M</a><t>dr</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FST</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value</brief></note>
</entry>
<entry mem_format="10" fpop="once" mod="mem">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FSTP</mnem><dst><a>M</a><t>dr</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FSTP</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mod="mem">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FRSTOR</mnem>
<dst nr="0" group="x87fpu" displayed="no">ST</dst>
<dst nr="1" group="x87fpu" displayed="no">ST1</dst>
<dst nr="2" group="x87fpu" displayed="no">ST2</dst>
<dst nr="3" group="x87fpu" displayed="no">ST3</dst>
<dst nr="4" group="x87fpu" displayed="no">ST4</dst>
<dst nr="5" group="x87fpu" displayed="no">ST5</dst>
<dst nr="6" group="x87fpu" displayed="no">ST6</dst>
<dst nr="7" group="x87fpu" displayed="no">ST7</dst>
<src><a>M</a><t>st</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Restore x87 FPU State</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>4</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem>FUCOM</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E1</sec_opcd>
<proc_start>03</proc_start>
<syntax>
<mnem>FUCOM</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" address="EST" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once">
<opcd_ext>5</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem>FUCOMP</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>E9</sec_opcd>
<proc_start>03</proc_start>
<syntax>
<mnem>FUCOMP</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" address="EST" displayed="no">ST1</src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values and Pop</brief></note>
</entry>
<!--<entry mod="mem">-->
<entry>
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FNSAVE</mnem>
<dst><a>M</a><t>st</t></dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
<src nr="2" group="x87fpu" displayed="no">ST2</src>
<src nr="3" group="x87fpu" displayed="no">ST3</src>
<src nr="4" group="x87fpu" displayed="no">ST4</src>
<src nr="5" group="x87fpu" displayed="no">ST5</src>
<src nr="6" group="x87fpu" displayed="no">ST6</src>
<src nr="7" group="x87fpu" displayed="no">ST7</src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<f_vals_fpu>abcd</f_vals_fpu>
<note><brief>Store x87 FPU State</brief></note>
</entry>
<!--<entry mod="mem">-->
<entry>
<opcd_ext>6</opcd_ext>
<pref>9B</pref>
<syntax>
<mnem>FSAVE</mnem>
<dst><a>M</a><t>st</t></dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
<src nr="2" group="x87fpu" displayed="no">ST2</src>
<src nr="3" group="x87fpu" displayed="no">ST3</src>
<src nr="4" group="x87fpu" displayed="no">ST4</src>
<src nr="5" group="x87fpu" displayed="no">ST5</src>
<src nr="6" group="x87fpu" displayed="no">ST6</src>
<src nr="7" group="x87fpu" displayed="no">ST7</src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<f_vals_fpu>abcd</f_vals_fpu>
<note><brief>Store x87 FPU State</brief></note>
</entry>
<!--<entry mod="mem">-->
<entry>
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FNSTSW</mnem><dst><a>M</a><t>w</t></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Status Word</brief></note>
</entry>
<!--<entry mod="mem">-->
<entry>
<opcd_ext>7</opcd_ext>
<pref>9B</pref>
<syntax>
<mnem>FSTSW</mnem><dst><a>M</a><t>w</t></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Status Word</brief></note>
</entry>
</pri_opcd>
<!-- DE -->
<pri_opcd value="DE">
<entry mem_format="11" mod="mem">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FIADD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FADDP</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>0</opcd_ext>
<sec_opcd>C1</sec_opcd>
<syntax>
<mnem>FADDP</mnem>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Add and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>1</opcd_ext>
<syntax>
<mnem>FIMUL</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>1</opcd_ext>
<syntax>
<mnem>FMULP</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>1</opcd_ext>
<sec_opcd>C9</sec_opcd>
<syntax>
<mnem>FMULP</mnem>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Multiply and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FICOM</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Integer</brief></note>
</entry>
<entry mod="nomem" alias="D8_3"
doc_ref="gen_note_FCOMP3_DC_3_FCOMP5_DE_2" fpop="once"
particular="yes">
<opcd_ext>2</opcd_ext>
<proc_end>02</proc_end>
<syntax>
<mnem sug="yes">FCOMP5</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D8_3" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" fpop="once"
particular="yes">
<opcd_ext>2</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem sug="yes">FCOMP5</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop</brief></note>
</entry>
<!--<entry mem_format="11" mod="mem" fpop="once">-->
<entry mem_format="11" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FICOMP</mnem><src nr="0" group="x87fpu" displayed="no">ST</src><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Integer and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="twice">-->
<entry fpop="twice"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>3</opcd_ext>
<sec_opcd>D9</sec_opcd>
<syntax>
<mnem>FCOMPP</mnem>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src> <!-- no @address="EST"! -->
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>0123</def_f_fpu>
<note><brief>Compare Real and Pop Twice</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FISUB</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FSUBRP</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E1</sec_opcd>
<syntax>
<mnem>FSUBRP</mnem>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FISUBR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Subtract</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FSUBP</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>5</opcd_ext>
<sec_opcd>E9</sec_opcd>
<syntax>
<mnem>FSUBP</mnem>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Subtract and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FIDIV</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FDIVRP</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>6</opcd_ext>
<sec_opcd>F1</sec_opcd>
<syntax>
<mnem>FDIVRP</mnem>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FIDIVR</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Reverse Divide</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FDIVP</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide and Pop</brief></note>
</entry>
<!--<entry mod="nomem" fpop="once">-->
<entry fpop="once"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>F9</sec_opcd>
<syntax>
<mnem>FDIVP</mnem>
<dst nr="1" group="x87fpu" address="EST" displayed="no">ST1</dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>arith</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Divide and Pop</brief></note>
</entry>
</pri_opcd>
<!-- DF -->
<pri_opcd value="DF">
<entry mem_format="11" mod="mem" fpush="yes">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>FILD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>wi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Integer</brief></note>
</entry>
<entry mod="nomem" doc_ref="gen_note_FFREEP_DF_1" fpop="once">
<opcd_ext>0</opcd_ext>
<syntax>
<mnem sug="yes">FFREEP</mnem><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Free Floating-Point Register and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem" fpop="once">
<opcd_ext>1</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>FISTTP</mnem><dst><a>M</a><t>wi</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>x87fpu</grp1>
<!-- 1.02--> <!--<grp2>conv</grp2>-->
<grp2>conver</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<f_vals_fpu>b</f_vals_fpu>
<note><brief>Store Integer with Truncation and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D9_1"
doc_ref="gen_note_FXCH4_DD_1_FXCH7_DF_1" particular="yes">
<opcd_ext>1</opcd_ext>
<proc_end>02</proc_end>
<syntax>
<mnem sug="yes">FXCH7</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><dst><a>EST</a></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Exchange Register Contents</brief></note>
</entry>
<entry mod="nomem" alias="D9_1" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" particular="yes">
<opcd_ext>1</opcd_ext>
<proc_start>03</proc_start>
<syntax>
<mnem sug="yes">FXCH7</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><dst><a>EST</a></dst>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Exchange Register Contents</brief></note>
</entry>
<entry mem_format="11" mod="mem">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>FIST</mnem><dst><a>M</a><t>wi</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Integer</brief></note>
</entry>
<entry mod="nomem" alias="D9_3"
doc_ref="gen_note_FSTP1_D9_3_FSTP8_DF_2_FSTP9_DF_3"
fpop="once" particular="yes">
<opcd_ext>2</opcd_ext>
<proc_end>02</proc_end>
<!--<syntax mod="mem">-->
<syntax>
<mnem sug="yes">FSTP8</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D9_3" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" fpop="once"
particular="yes">
<opcd_ext>2</opcd_ext>
<proc_start>03</proc_start>
<!--<syntax mod="mem">-->
<syntax>
<mnem sug="yes">FSTP8</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mem_format="11" mod="mem" fpop="once">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>FISTP</mnem><dst><a>M</a><t>wi</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Integer and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D9_3"
doc_ref="gen_note_FSTP1_D9_3_FSTP8_DF_2_FSTP9_DF_3"
fpop="once" particular="yes">
<opcd_ext>3</opcd_ext>
<proc_end>02</proc_end>
<!--<syntax mod="mem">-->
<syntax>
<mnem sug="yes">FSTP9</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<entry mod="nomem" alias="D9_3" doc="u"
doc_ref="gen_note_x87_fpu_undoc_aliases" fpop="once"
particular="yes">
<opcd_ext>3</opcd_ext>
<proc_start>03</proc_start>
<!--<syntax mod="mem">-->
<syntax>
<mnem sug="yes">FSTP9</mnem><dst><a>EST</a></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Floating Point Value and Pop</brief></note>
</entry>
<!--<entry mod="mem" fpush="yes">-->
<entry fpush="yes">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>FBLD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>bcd</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Binary Coded Decimal</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<sec_opcd>E0</sec_opcd>
<proc_start>02</proc_start>
<syntax>
<mnem>FNSTSW</mnem><dst nr="0" group="gen" type="w" depend="no">AX</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Status Word</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>4</opcd_ext>
<pref>9B</pref>
<sec_opcd>E0</sec_opcd>
<proc_start>02</proc_start>
<syntax>
<mnem>FSTSW</mnem><dst nr="0" group="gen" type="w" depend="no">AX</dst>
</syntax>
<grp1>x87fpu</grp1><grp2>control</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<undef_f_fpu>0123</undef_f_fpu>
<note><brief>Store x87 FPU Status Word</brief></note>
</entry>
<entry mod="mem" fpush="yes">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>FILD</mnem><dst nr="0" group="x87fpu" displayed="no">ST</dst><src><a>M</a><t>qi</t></src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Load Integer</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>5</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FUCOMIP</mnem><src nr="0" group="x87fpu">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f>ozpc</modif_f>
<def_f>ozpc</def_f>
<f_vals>o</f_vals>
<modif_f_fpu>1</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<note><brief>Unordered Compare Floating Point Values and Set EFLAGS and Pop</brief></note>
</entry>
<entry mod="mem" fpop="once">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>FBSTP</mnem><dst><a>M</a><t>bcd</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store BCD Integer and Pop</brief></note>
</entry>
<entry mod="nomem" fpop="once">
<opcd_ext>6</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>FCOMIP</mnem><src nr="0" group="x87fpu">ST</src><src><a>EST</a></src>
</syntax>
<grp1>x87fpu</grp1><grp2>compar</grp2>
<modif_f>ozpc</modif_f>
<def_f>ozpc</def_f>
<f_vals>o</f_vals>
<modif_f_fpu>1</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<note><brief>Compare Floating Point Values and Set EFLAGS and Pop</brief></note>
</entry>
<!--<entry mod="mem" fpop="once">-->
<entry fpop="once">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>FISTP</mnem><dst><a>M</a><t>qi</t></dst><src nr="0" group="x87fpu" displayed="no">ST</src>
</syntax>
<grp1>x87fpu</grp1><grp2>datamov</grp2>
<modif_f_fpu>0123</modif_f_fpu>
<def_f_fpu>1</def_f_fpu>
<undef_f_fpu>023</undef_f_fpu>
<note><brief>Store Integer and Pop</brief></note>
</entry>
</pri_opcd>
<!-- E0 -->
<pri_opcd value="E0">
<entry>
<syntax>
<mnem>LOOPNZ</mnem>
<!-- <dst nr="1" group="gen" type="vaqp" displayed="no">rCX</dst>-->
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<syntax>
<mnem>LOOPNE</mnem>
<!-- <dst nr="1" group="gen" type="vaqp" displayed="no">rCX</dst>-->
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Decrement count; Jump short if count!=0 and ZF=0</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>LOOPNZ</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<syntax>
<mnem>LOOPNE</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Decrement count; Jump short if count!=0 and ZF=0</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E1">
<entry>
<syntax>
<mnem>LOOPZ</mnem>
<!-- <dst nr="1" group="gen" type="vaqp" displayed="no">rCX</dst>-->
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<syntax>
<mnem>LOOPE</mnem>
<!-- <dst nr="1" group="gen" type="vaqp" displayed="no">rCX</dst>-->
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Decrement count; Jump short if count!=0 and ZF=1</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>LOOPZ</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<syntax>
<mnem>LOOPE</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Decrement count; Jump short if count!=0 and ZF=1</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E2">
<entry>
<syntax>
<mnem>LOOP</mnem>
<!-- <dst nr="1" group="gen" type="vaqp" displayed="no">rCX</dst>-->
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Decrement count; Jump short if count!=0</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>LOOP</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
<src><a>J</a><t>bs</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Decrement count; Jump short if count!=0</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E3">
<entry>
<syntax>
<mnem>JCXZ</mnem>
<src><a>J</a><t>bs</t></src>
<src nr="1" group="gen" type="wa" displayed="no">CX</src>
</syntax>
<syntax>
<mnem>JECXZ</mnem>
<src><a>J</a><t>bs</t></src>
<src nr="1" group="gen" type="da" displayed="no">ECX</src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Jump short if eCX register is 0</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>JECXZ</mnem>
<src><a>J</a><t>bs</t></src>
<src nr="1" group="gen" type="da" displayed="no">ECX</src>
</syntax>
<syntax>
<mnem>JRCXZ</mnem>
<src><a>J</a><t>bs</t></src>
<src nr="1" group="gen" type="qa" displayed="no">RCX</src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<note><brief>Jump short if rCX register is 0</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E4">
<entry op_size="0" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>IN</mnem>
<dst nr="0" group="gen" type="b" depend="no">AL</dst>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Input from Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E5">
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>IN</mnem>
<dst nr="0" group="gen" type="v" depend="no">eAX</dst>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Input from Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E6">
<entry op_size="0" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>OUT</mnem>
<dst><a>I</a><t>b</t></dst>
<src nr="0" group="gen" type="b">AL</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Output to Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E7">
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>OUT</mnem>
<dst><a>I</a><t>b</t></dst>
<src nr="0" group="gen" type="v" depend="no">eAX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Output to Port</brief></note>
</entry>
</pri_opcd>
<!-- 1.02
<pri_opcd value="E8">
<entry>
<syntax><mnem>CALL</mnem><src><a>J</a><t>v</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<proc_start>10</proc_start>
<syntax><mnem>CALL</mnem><src><a>J</a><t>ds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
</pri_opcd>
-->
<pri_opcd value="E8">
<entry doc64_ref="gen_note_short_near_jmp">
<syntax>
<mnem>CALL</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>J</a><t>vds</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
</pri_opcd>
<!-- 1.02
<pri_opcd value="E9">
<entry>
<syntax><mnem>JMP</mnem><src><a>J</a><t>v</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<proc_start>10</proc_start>
<syntax><mnem>JMP</mnem><src><a>J</a><t>ds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
</pri_opcd>
-->
<pri_opcd value="E9">
<entry doc64_ref="gen_note_short_near_jmp">
<syntax><mnem>JMP</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EA">
<entry>
<syntax><mnem>JMPF</mnem><src><a>A</a><t>p</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
<entry attr="invd" mode="e">
<proc_start>10</proc_start>
<syntax/>
<note><brief>Invalid Instruction in 64-Bit Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EB">
<entry>
<syntax><mnem>JMP</mnem><src><a>J</a><t>bs</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EC">
<entry op_size="0" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>IN</mnem>
<dst nr="0" group="gen" type="b" depend="no">AL</dst>
<src nr="2" group="gen" type="w">DX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Input from Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="ED">
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>IN</mnem>
<dst nr="0" group="gen" type="v" depend="no">eAX</dst>
<src nr="2" group="gen" type="w">DX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Input from Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EE">
<entry op_size="0" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>OUT</mnem>
<dst nr="2" group="gen" type="w">DX</dst>
<src nr="0" group="gen" type="b">AL</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Output to Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EF">
<entry op_size="1" ring="f" ring_ref="rflags_iopl">
<syntax>
<mnem>OUT</mnem>
<dst nr="2" group="gen" type="w">DX</dst>
<src nr="0" group="gen" type="v" depend="no">eAX</src>
</syntax>
<grp1>gen</grp1><grp2>inout</grp2>
<note><brief>Output to Port</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F0">
<entry>
<syntax><mnem>LOCK</mnem></syntax>
<grp1>prefix</grp1>
<note><brief>Assert LOCK# Signal Prefix</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F1">
<entry attr="undef" is_undoc="yes"
doc_ref="gen_note_undefined_D6_F1">
<syntax/>
<note><brief>Undefined and Reserved; Does not Generate #UD</brief></note>
</entry>
<entry part_alias="CD"
doc_part_alias_ref="gen_note_u_INT1_ICEBP_F1" doc="u"
is_doc="yes" doc_ref="gen_note_u_INT1_ICEBP_F1">
<proc_start>03</proc_start>
<syntax>
<mnem>INT1</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="v" address="F" displayed="no">eFlags</src>
</syntax>
<syntax>
<mnem>ICEBP</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src type="v" address="F" displayed="no">eFlags</src>
</syntax>
<grp1>gen</grp1><grp2>break</grp2><grp2>stack</grp2>
<!-- <test_f>odiszapc</test_f>-->
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Call to Interrupt Procedure</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F2">
<entry doc_ref="gen_note_REP_F2_F3">
<syntax>
<mnem>REPNZ</mnem>
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
</syntax>
<syntax>
<mnem>REPNE</mnem>
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<test_f>z</test_f>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc="u" doc_ref="gen_note_REP_F2_F3" particular="yes">
<syntax>
<mnem>REP</mnem>
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc_ref="gen_note_REP_F2_F3" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>REPNZ</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
</syntax>
<syntax>
<mnem>REPNE</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<test_f>z</test_f>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc="u" doc_ref="gen_note_REP_F2_F3" mode="e"
particular="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>REP</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc="m">
<proc_start>10</proc_start>
<syntax/>
<instr_ext>sse2</instr_ext>
<grp1>prefix</grp1>
<note><brief>Scalar Double-precision Prefix</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F3">
<entry doc_ref="gen_note_REP_F2_F3">
<syntax>
<mnem>REPZ</mnem>
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
</syntax>
<syntax>
<mnem>REPE</mnem>
<dst nr="1" group="gen" type="va" displayed="no">eCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<test_f>z</test_f>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc_ref="gen_note_REP_F2_F3">
<syntax>
<mnem>REP</mnem>
<dst nr="1" group="gen" type="va" displayed="no">rCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc_ref="gen_note_REP_F2_F3" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>REPZ</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
</syntax>
<syntax>
<mnem>REPE</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<test_f>z</test_f>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc_ref="gen_note_REP_F2_F3" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>REP</mnem>
<dst nr="1" group="gen" type="dqa" displayed="no">rCX</dst>
</syntax>
<grp1>prefix</grp1><grp2>string</grp2>
<note><brief>Repeat String Operation Prefix</brief></note>
</entry>
<entry doc="m">
<proc_start>09</proc_start>
<syntax/>
<instr_ext>sse1</instr_ext>
<grp1>prefix</grp1>
<note><brief>Scalar Single-precision Prefix</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F4">
<entry ring="0">
<syntax><mnem>HLT</mnem></syntax>
<grp1>system</grp1>
<note><brief>Halt</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F5">
<entry>
<syntax><mnem>CMC</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<test_f>c</test_f><modif_f>c</modif_f><def_f>c</def_f>
<note><brief>Complement Carry Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F6">
<entry op_size="0">
<opcd_ext>0</opcd_ext>
<syntax><mnem>TEST</mnem><src><a>E</a><t>b</t></src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
<entry op_size="0" alias="F6_0" doc="u" doc_ref="gen_note_TEST_F6_1_F7_1">
<opcd_ext>1</opcd_ext>
<syntax><mnem>TEST</mnem><src><a>E</a><t>b</t></src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>2</opcd_ext>
<syntax><mnem>NOT</mnem><dst><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<note><brief>One's Complement Negation</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>3</opcd_ext>
<syntax><mnem>NEG</mnem><dst><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Two's Complement Negation</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>MUL</mnem>
<dst nr="0" group="gen" type="w" displayed="no">AX</dst>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
<src><a>E</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Unsigned Multiply</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>IMUL</mnem>
<dst nr="0" group="gen" type="w" displayed="no">AX</dst>
<src nr="0" group="gen" type="b" displayed="no">AL</src>
<src><a>E</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Signed Multiply</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>DIV</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no">AH</dst>
<src nr="0" group="gen" type="w" displayed="no">AX</src>
<src><a>E</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Unsigned Divide</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>IDIV</mnem>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<dst nr="4" group="gen" type="b" displayed="no">AH</dst>
<src nr="0" group="gen" type="w" displayed="no">AX</src>
<src><a>E</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Signed Divide</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F7">
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax><mnem>TEST</mnem><src><a>E</a><t>vqp</t></src><src><a>I</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
<entry op_size="1" alias="F7_0" doc="u" doc_ref="gen_note_TEST_F6_1_F7_1">
<opcd_ext>1</opcd_ext>
<syntax><mnem>TEST</mnem><src><a>E</a><t>vqp</t></src><src><a>I</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>a</undef_f><f_vals>oc</f_vals>
<note><brief>Logical Compare</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>2</opcd_ext>
<syntax><mnem>NOT</mnem><dst><a>E</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1><grp2>logical</grp2>
<note><brief>One's Complement Negation</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>3</opcd_ext>
<syntax><mnem>NEG</mnem><dst><a>E</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Two's Complement Negation</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>4</opcd_ext>
<syntax>
<mnem>MUL</mnem>
<dst nr="2" group="gen" type="vqp" depend="no" displayed="no">rDX</dst>
<dst nr="0" group="gen" type="vqp" displayed="no">rAX</dst>
<src><a>E</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Unsigned Multiply</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>5</opcd_ext>
<syntax>
<mnem>IMUL</mnem>
<dst nr="2" group="gen" type="vqp" depend="no" displayed="no">rDX</dst>
<dst nr="0" group="gen" type="vqp" displayed="no">rAX</dst>
<src><a>E</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Signed Multiply</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>DIV</mnem>
<dst nr="2" group="gen" type="vqp" displayed="no">rDX</dst>
<dst nr="0" group="gen" type="vqp" displayed="no">rAX</dst>
<src><a>E</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Unsigned Divide</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>7</opcd_ext>
<syntax>
<mnem>IDIV</mnem>
<dst nr="2" group="gen" type="vqp" displayed="no">rDX</dst>
<dst nr="0" group="gen" type="vqp" displayed="no">rAX</dst>
<src><a>E</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Signed Divide</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F8">
<entry>
<syntax><mnem>CLC</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<modif_f>c</modif_f><def_f>c</def_f><f_vals>c</f_vals>
<note><brief>Clear Carry Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F9">
<entry>
<syntax><mnem>STC</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<modif_f>c</modif_f><def_f>c</def_f><f_vals>C</f_vals>
<note><brief>Set Carry Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FA">
<entry ring="f" ring_ref="rflags_iopl">
<syntax><mnem>CLI</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Clear Interrupt Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FB">
<entry attr="delaysint_cond" ring="f" ring_ref="rflags_iopl">
<syntax><mnem>STI</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<modif_f>i</modif_f><def_f>i</def_f><f_vals>I</f_vals>
<note><brief>Set Interrupt Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FC">
<entry>
<syntax><mnem>CLD</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<modif_f>d</modif_f><def_f>d</def_f><f_vals>d</f_vals>
<note><brief>Clear Direction Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FD">
<entry>
<syntax><mnem>STD</mnem></syntax>
<grp1>gen</grp1><grp2>flgctrl</grp2>
<modif_f>d</modif_f><def_f>d</def_f><f_vals>D</f_vals>
<note><brief>Set Direction Flag</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FE">
<entry op_size="0">
<opcd_ext>0</opcd_ext>
<syntax><mnem>INC</mnem><dst><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszap</modif_f><def_f>oszap</def_f>
<note><brief>Increment by 1</brief></note>
</entry>
<entry op_size="0">
<opcd_ext>1</opcd_ext>
<syntax><mnem>DEC</mnem><dst><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszap</modif_f><def_f>oszap</def_f>
<note><brief>Decrement by 1</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FF">
<entry op_size="1">
<opcd_ext>0</opcd_ext>
<syntax><mnem>INC</mnem><dst><a>E</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszap</modif_f><def_f>oszap</def_f>
<note><brief>Increment by 1</brief></note>
</entry>
<entry op_size="1">
<opcd_ext>1</opcd_ext>
<syntax><mnem>DEC</mnem><dst><a>E</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszap</modif_f><def_f>oszap</def_f>
<note><brief>Decrement by 1</brief></note>
</entry>
<entry> <!-- op_size="1" removed in 1.01 -->
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>CALL</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<opcd_ext>2</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>CALL</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>E</a><t>q</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
<entry doc64_ref="gen_note_CALLF_FF_3_JMPF_FF_5"> <!-- op_size="1" removed in 1.01 -->
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>CALLF</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>M</a><t>ptp</t></src>
</syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp2>stack</grp2>
<note><brief>Call Procedure</brief></note>
</entry>
<entry> <!-- op_size="1" removed in 1.01 -->
<opcd_ext>4</opcd_ext>
<syntax><mnem>JMP</mnem><src><a>E</a><t>v</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
<entry doc64_ref="gen_note_short_near_jmp" mode="e">
<opcd_ext>4</opcd_ext>
<proc_start>10</proc_start>
<syntax><mnem>JMP</mnem><src><a>E</a><t>q</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
<entry doc64_ref="gen_note_CALLF_FF_3_JMPF_FF_5"> <!-- op_size="1" removed in 1.01 -->
<opcd_ext>5</opcd_ext>
<syntax><mnem>JMPF</mnem><src><a>M</a><t>ptp</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2>
<note><brief>Jump</brief></note>
</entry>
<entry> <!-- op_size="1" removed in 1.01 -->
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
<entry mode="e"> <!-- op_size="1" removed in 1.01 -->
<opcd_ext>6</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src><a>E</a><t>vq</t></src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
</pri_opcd>
</one-byte>
<two-byte xml:id="two-byte">
<pri_opcd value="00">
<proc_start>02</proc_start>
<entry mode="p">
<opcd_ext>0</opcd_ext>
<syntax mod="mem">
<mnem>SLDT</mnem>
<dst depend="no"><a>M</a><t>w</t></dst>
<src group="systabp" displayed="no">LDTR</src>
</syntax>
<syntax mod="nomem">
<mnem>SLDT</mnem>
<dst depend="no"><a>R</a><t>vqp</t></dst>
<src group="systabp" displayed="no">LDTR</src>
</syntax>
<grp1>system</grp1>
<note><brief>Store Local Descriptor Table Register</brief></note>
</entry>
<entry mode="p">
<opcd_ext>1</opcd_ext>
<syntax mod="mem">
<mnem>STR</mnem>
<dst depend="no"><a>M</a><t>w</t></dst>
<src group="systabp" displayed="no">TR</src>
</syntax>
<syntax mod="nomem">
<mnem>STR</mnem>
<dst depend="no"><a>R</a><t>vqp</t></dst>
<src group="systabp" displayed="no">TR</src>
</syntax>
<grp1>system</grp1>
<note><brief>Store Task Register</brief></note>
</entry>
<entry attr="serial" ring="0" mode="p">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>LLDT</mnem>
<dst group="systabp" displayed="no" depend="no">LDTR</dst>
<src><a>E</a><t>w</t></src>
</syntax>
<grp1>system</grp1>
<note><brief>Load Local Descriptor Table Register</brief></note>
</entry>
<entry attr="serial" ring="0" mode="p">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>LTR</mnem>
<dst group="systabp" displayed="no" depend="no">TR</dst>
<src><a>E</a><t>w</t></src>
</syntax>
<grp1>system</grp1>
<note><brief>Load Task Register</brief></note>
</entry>
<entry mode="p">
<opcd_ext>4</opcd_ext>
<syntax><mnem>VERR</mnem><src><a>E</a><t>w</t></src></syntax>
<grp1>system</grp1>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Verify a Segment for Reading</brief></note>
</entry>
<entry mode="p">
<opcd_ext>5</opcd_ext>
<syntax><mnem>VERW</mnem><src><a>E</a><t>w</t></src></syntax>
<grp1>system</grp1>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Verify a Segment for Writing</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<proc_start>99</proc_start>
<syntax><mnem>JMPE</mnem></syntax>
<grp1>system</grp1><grp2>branch</grp2>
<note><brief>Jump to IA-64 Instruction Set</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="01">
<proc_start>02</proc_start>
<entry>
<opcd_ext>0</opcd_ext>
<syntax>
<mnem>SGDT</mnem>
<dst depend="no"><a>M</a><t>s</t></dst>
<src group="systabp" displayed="no">GDTR</src>
</syntax>
<grp1>system</grp1>
<note><brief>Store Global Descriptor Table Register</brief></note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<opcd_ext>0</opcd_ext>
<sec_opcd>C1</sec_opcd>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMCALL</mnem>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>
<grp2>branch</grp2>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Call to VM Monitor</brief>
<det>Call to VM monitor by causing VM exit</det>
</note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<opcd_ext>0</opcd_ext>
<sec_opcd>C2</sec_opcd>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMLAUNCH</mnem>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Launch Virtual Machine</brief>
<det>Launch virtual machine managed by current VMCS</det>
</note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<opcd_ext>0</opcd_ext>
<sec_opcd>C3</sec_opcd>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMRESUME</mnem>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Resume Virtual Machine</brief>
<det>Resume virtual machine managed by current VMCS</det>
</note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<opcd_ext>0</opcd_ext>
<sec_opcd>C4</sec_opcd>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMXOFF</mnem>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Leave VMX Operation</brief>
<det>Leaves VMX operation</det>
</note>
</entry>
<entry>
<opcd_ext>1</opcd_ext>
<syntax>
<mnem>SIDT</mnem>
<dst depend="no"><a>M</a><t>s</t></dst>
<src group="systabp" displayed="no">IDTR</src>
</syntax>
<grp1>system</grp1>
<note><brief>Store Interrupt Descriptor Table Register</brief></note>
</entry>
<entry ring="0"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>1</opcd_ext>
<sec_opcd>C8</sec_opcd>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>MONITOR</mnem>
<src type="b" address="BA" depend="no" displayed="no">(DS:)[rAX]</src>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>sync</grp1>
<note><brief>Set Up Monitor Address</brief></note>
</entry>
<entry ring="0"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>1</opcd_ext>
<sec_opcd>C9</sec_opcd>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>MWAIT</mnem>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>sync</grp1>
<note><brief>Monitor Wait</brief></note>
</entry>
<entry attr="serial" ring="0">
<opcd_ext>2</opcd_ext>
<syntax>
<mnem>LGDT</mnem>
<dst group="systabp" depend="no" displayed="no">GDTR</dst>
<src><a>M</a><t>s</t></src>
</syntax>
<grp1>system</grp1>
<note><brief>Load Global Descriptor Table Register</brief></note>
</entry>
<entry> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>2</opcd_ext>
<sec_opcd>D0</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>XGETBV</mnem>
<dst nr="2" group="gen" type="d" depend="no" displayed="no">EDX</dst>
<dst nr="0" group="gen" type="d" depend="no" displayed="no">EAX</dst>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
<src group="xcr" displayed="no">XCR</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Get Value of Extended Control Register</brief>
<det>Reads an XCR specified by ECX into EDX:EAX</det>
</note>
</entry>
<entry ring="0"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>2</opcd_ext>
<sec_opcd>D1</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>XSETBV</mnem>
<dst group="xcr" depend="no" displayed="no">XCR</dst>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Set Extended Control Register</brief>
<det>Write the value in EDX:EAX to the XCR specified by ECX</det>
</note>
</entry>
<entry attr="serial" ring="0">
<opcd_ext>3</opcd_ext>
<syntax>
<mnem>LIDT</mnem>
<dst group="systabp" depend="no" displayed="no">IDTR</dst>
<src><a>M</a><t>s</t></src>
</syntax>
<grp1>system</grp1>
<note><brief>Load Interrupt Descriptor Table Register</brief></note>
</entry>
<entry doc_ref="gen_note_SMSW_0F01_4">
<opcd_ext>4</opcd_ext>
<syntax mod="mem">
<mnem>SMSW</mnem>
<dst depend="no"><a>M</a><t>w</t></dst>
<src nr="0" group="ctrl" type="w" displayed="no">MSW</src>
</syntax>
<syntax mod="nomem">
<mnem>SMSW</mnem>
<dst depend="no"><a>R</a><t>vqp</t></dst>
<src nr="0" group="ctrl" type="w" displayed="no">MSW</src>
</syntax>
<grp1>system</grp1>
<note><brief>Store Machine Status Word</brief></note>
</entry>
<entry attr="serial" ring="0">
<!-- LMSW is valid in real-address mode -->
<opcd_ext>6</opcd_ext>
<syntax>
<mnem>LMSW</mnem>
<dst nr="0" group="ctrl" type="w" displayed="no" depend="no">MSW</dst>
<src><a>E</a><t>w</t></src>
</syntax>
<grp1>system</grp1>
<note><brief>Load Machine Status Word</brief></note>
</entry>
<entry attr="serial" ring="0">
<!-- INVLPG is valid in real-address mode; -->
<!-- the operand has no type because it doesn't really touch memory -->
<opcd_ext>7</opcd_ext>
<proc_start>04</proc_start>
<syntax>
<mnem>INVLPG</mnem>
<src depend="no"><a>M</a></src>
</syntax>
<grp1>system</grp1>
<note><brief>Invalidate TLB Entry</brief></note>
</entry>
<entry ring="0" mode="e"> <!-- @mod=nomem not needed, because sec_opcd must be matched -->
<opcd_ext>7</opcd_ext>
<sec_opcd>F8</sec_opcd>
<proc_start>10</proc_start>
<syntax>
<mnem>SWAPGS</mnem>
<dst nr="5" group="seg" type="w" displayed="no">GS</dst>
<dst nr="C0000102" group="msr" displayed="no">IA32_KERNEL_GSBASE</dst>
</syntax>
<grp1>system</grp1>
<note><brief>Swap GS Base Register</brief></note>
</entry>
<entry attr="serial" ring="f" ring_ref="cr4_tsd">
<opcd_ext>7</opcd_ext>
<sec_opcd>F9</sec_opcd>
<proc_start>13</proc_start>
<syntax>
<mnem>RDTSCP</mnem>
<dst nr="0" group="gen" type="d" depend="no" displayed="no">EAX</dst>
<dst nr="2" group="gen" type="d" depend="no" displayed="no">EDX</dst>
<dst nr="1" group="gen" type="d" depend="no" displayed="no">ECX</dst>
<src nr="10" group="msr" displayed="no">IA32_TIME_STAMP_COUNTER</src>
<src nr="C0000103" group="msr" displayed="no">IA32_TSC_AUX</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Read Time-Stamp Counter and Processor ID</brief>
<det>Read 64-bit time-stamp counter and 32-bit IA32_TSC_AUX value into EDX:EAX and ECX</det>
</note>
</entry>
</pri_opcd>
<pri_opcd value="02">
<entry r="yes" mode="p">
<proc_start>02</proc_start>
<syntax mod="mem"><mnem>LAR</mnem><dst><a>G</a><t>vqp</t></dst><src><a>M</a><t>w</t></src></syntax>
<syntax mod="nomem"><mnem>LAR</mnem><dst><a>G</a><t>vqp</t></dst><src><a>R</a><t>v</t></src></syntax>
<grp1>system</grp1>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Load Access Rights Byte</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="03">
<entry r="yes" mode="p">
<proc_start>02</proc_start>
<syntax mod="mem"><mnem>LSL</mnem><dst><a>G</a><t>vqp</t></dst><src><a>M</a><t>w</t></src></syntax>
<syntax mod="nomem"><mnem>LSL</mnem><dst><a>G</a><t>vqp</t></dst><src><a>R</a><t>v</t></src></syntax>
<grp1>system</grp1>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Load Segment Limit</brief></note>
</entry>
</pri_opcd>
<!-- 0F04: according to sandpile.org, the semantic is not clear,
therefore remains invalid -->
<pri_opcd value="05">
<entry doc="u" doc1632_ref="gen_note_u_LOADALL_0F05_0F07" mode="p"
particular="yes">
<proc_start post="no">02</proc_start>
<proc_end>02</proc_end>
<syntax>
<mnem>LOADALL</mnem>
<dst nr="0" group="gen" type="w" depend="no" displayed="no">AX</dst>
<dst nr="1" group="gen" type="w" depend="no" displayed="no">CX</dst>
<dst nr="2" group="gen" type="w" depend="no" displayed="no">DX</dst>
<dst nr="3" group="gen" type="w" depend="no" displayed="no">BX</dst>
<dst nr="4" group="gen" type="w" depend="no" displayed="no">SP</dst>
<dst nr="5" group="gen" type="w" depend="no" displayed="no">BP</dst>
<dst nr="6" group="gen" type="w" depend="no" displayed="no">SI</dst>
<dst nr="7" group="gen" type="w" depend="no" displayed="no">DI</dst>
<dst type="w" address="F" depend="no" displayed="no">Flags</dst>
<dst nr="0" group="seg" type="w" depend="no" displayed="no">ES</dst>
<dst nr="2" group="seg" type="w" depend="no" displayed="no">SS</dst>
<dst nr="3" group="seg" type="w" depend="no" displayed="no">DS</dst>
<dst nr="0" group="ctrl" type="w" displayed="no" depend="no">MSW</dst>
<dst group="systabp" displayed="no" depend="no">TR</dst>
<dst group="systabp" displayed="no" depend="no">LDTR</dst>
<dst group="systabp" displayed="no" depend="no">GDTR</dst>
<dst group="systabp" displayed="no" depend="no">IDTR</dst>
</syntax>
<grp1>system</grp1><grp2>branch</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Load All of the CPU Registers</brief></note>
</entry>
<entry doc64_ref="gen_note_SYSCALL_0F05" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>SYSCALL</mnem>
<dst nr="1" group="gen" type="q" depend="no" displayed="no">RCX</dst>
<dst nr="11" group="gen" type="q" depend="no" displayed="no">R11</dst>
<dst nr="2" group="seg" type="w" depend="no" displayed="no">SS</dst>
<!-- syscall does not really depend on EFLAGS, it only saves its value -->
<src type="d" address="F" depend="no" displayed="no">EFlags</src>
<src nr="C0000082" group="msr" displayed="no">IA32_LSTAR</src>
<src nr="C0000084" group="msr" displayed="no">IA32_FMASK</src>
</syntax>
<grp1>system</grp1><grp2>branch</grp2>
<note><brief>Fast System Call</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="06">
<!-- <entry ring="0" mode="p">-->
<entry ring="0">
<proc_start>02</proc_start>
<syntax>
<mnem>CLTS</mnem>
<dst nr="0" group="ctrl" displayed="no">CR0</dst>
</syntax>
<grp1>system</grp1>
<note><brief>Clear Task-Switched Flag in CR0</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="07">
<entry doc="u" doc1632_ref="gen_note_u_LOADALL_0F05_0F07" mode="p"
particular="yes">
<proc_start post="no">03</proc_start>
<proc_end>03</proc_end>
<syntax>
<mnem>LOADALL</mnem>
<dst nr="0" group="gen" type="d" depend="no" displayed="no">EAX</dst>
<dst nr="1" group="gen" type="d" depend="no" displayed="no">ECX</dst>
<dst nr="2" group="gen" type="d" depend="no" displayed="no">EDX</dst>
<dst nr="3" group="gen" type="d" depend="no" displayed="no">EBX</dst>
<dst nr="4" group="gen" type="d" depend="no" displayed="no">ESP</dst>
<dst nr="5" group="gen" type="d" depend="no" displayed="no">EBP</dst>
<dst nr="6" group="gen" type="d" depend="no" displayed="no">ESI</dst>
<dst nr="7" group="gen" type="d" depend="no" displayed="no">EDI</dst>
<dst type="d" address="F" depend="no" displayed="no">EFlags</dst>
<dst nr="0" group="seg" type="w" depend="no" displayed="no">ES</dst>
<dst nr="2" group="seg" type="w" depend="no" displayed="no">SS</dst>
<dst nr="3" group="seg" type="w" depend="no" displayed="no">DS</dst>
<dst nr="4" group="seg" type="w" depend="no" displayed="no">FS</dst>
<dst nr="5" group="seg" type="w" depend="no" displayed="no">GS</dst>
<dst nr="0" group="ctrl" type="d" displayed="no" depend="no">CR0</dst>
<dst nr="6" group="debug" type="d" depend="no" displayed="no">DR6</dst>
<dst nr="7" group="debug" type="d" depend="no" displayed="no">DR7</dst>
<dst group="systabp" displayed="no" depend="no">TR</dst>
<dst group="systabp" displayed="no" depend="no">LDTR</dst>
<dst group="systabp" displayed="no" depend="no">GDTR</dst>
<dst group="systabp" displayed="no" depend="no">IDTR</dst>
</syntax>
<grp1>system</grp1><grp2>branch</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Load All of the CPU Registers</brief></note>
</entry>
<entry ring="0" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>SYSRET</mnem>
<dst nr="2" group="seg" type="w" depend="no" displayed="no">SS</dst>
<dst type="d" address="F" depend="no" displayed="no">EFlags</dst>
<src nr="11" group="gen" type="q" depend="no" displayed="no">R11</src>
<src nr="1" group="gen" type="q" depend="no" displayed="no">RCX</src>
<src nr="C0000081" group="msr" displayed="no">IA32_STAR</src>
</syntax>
<grp1>system</grp1><grp2>branch</grp2><grp3>trans</grp3>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Return From Fast System Call</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="08">
<entry attr="serial" ring="0">
<proc_start>04</proc_start>
<syntax><mnem>INVD</mnem></syntax>
<grp1>system</grp1>
<note><brief>Invalidate Internal Caches</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="09">
<entry attr="serial" ring="0">
<proc_start>04</proc_start>
<syntax><mnem>WBINVD</mnem></syntax>
<grp1>system</grp1>
<note><brief>Write Back and Invalidate Cache</brief></note>
</entry>
</pri_opcd>
<!-- 0F0A: invalid -->
<pri_opcd value="0B">
<entry attr="invd">
<proc_start>02</proc_start>
<syntax><mnem>UD2</mnem></syntax>
<grp1>gen</grp1><grp2>control</grp2>
<note><brief>Undefined Instruction</brief></note>
</entry>
</pri_opcd>
<!-- 0F0C: invalid -->
<pri_opcd value="0D">
<entry doc="m" doc_ref="gen_note_NOP_0F0D">
<proc_start>07</proc_start>
<syntax><mnem>NOP</mnem><src depend="no"><a>E</a><t>v</t></src></syntax>
<grp1>gen</grp1><grp2>control</grp2>
<note><brief>No Operation</brief></note>
</entry>
</pri_opcd>
<!-- 0F0E: 3DNow! FEMMS, Intel: invalid -->
<!-- 0F0F: 3DNow! group, Intel: invalid -->
<pri_opcd value="10">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVUPS</mnem>
<dst depend="no"><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Unaligned Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>MOVSS</mnem>
<dst depend="no"><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Scalar Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVUPD</mnem>
<dst depend="no"><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Unaligned Packed Double-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVSD</mnem>
<dst depend="no"><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Scalar Double-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="11">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVUPS</mnem>
<dst depend="no"><a>W</a><t>ps</t></dst>
<src><a>V</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Unaligned Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>MOVSS</mnem>
<dst depend="no"><a>W</a><t>ss</t></dst>
<src><a>V</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Scalar Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVUPD</mnem>
<dst depend="no"><a>W</a><t>pd</t></dst>
<src><a>V</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Unaligned Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVSD</mnem>
<dst depend="no"><a>W</a><t>sd</t></dst>
<src><a>V</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Scalar Double-FP Value</brief></note>
</entry>
</pri_opcd>
<!-- 0F12 -->
<pri_opcd value="12">
<entry r="yes" mod="nomem">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVHLPS</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>U</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Packed Single-FP Values High to Low</brief></note>
</entry>
<entry r="yes" mod="mem">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVLPS</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Low Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVLPD</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Low Packed Double-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>MOVDDUP</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>W</a><t>q</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move One Double-FP and Duplicate</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>MOVSLDUP</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>W</a><t>q</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Packed Single-FP Low and Duplicate</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="13">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVLPS</mnem>
<dst depend="no"><a>M</a><t>q</t></dst>
<src><a>V</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Low Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVLPD</mnem>
<dst depend="no"><a>M</a><t>q</t></dst>
<src><a>V</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Low Packed Double-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="14">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>UNPCKLPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack and Interleave Low Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>UNPCKLPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack and Interleave Low Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="15">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>UNPCKHPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack and Interleave High Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>UNPCKHPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack and Interleave High Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="16">
<entry r="yes" mod="nomem">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVLHPS</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>U</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Packed Single-FP Values Low to High</brief></note>
</entry>
<entry r="yes" mod="mem">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVHPS</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move High Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVHPD</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move High Packed Double-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>MOVSHDUP</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>W</a><t>q</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Packed Single-FP High and Duplicate</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="17">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVHPS</mnem>
<dst depend="no"><a>M</a><t>q</t></dst>
<src><a>V</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move High Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVHPD</mnem>
<dst depend="no"><a>M</a><t>q</t></dst>
<src><a>V</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move High Packed Double-FP Value</brief></note>
</entry>
</pri_opcd>
<!-- 0F18 -->
<pri_opcd value="18">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<proc_end>08</proc_end>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry>
<opcd_ext>0</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>PREFETCHNTA</mnem>
<src depend="no"><a>M</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>fetch</grp1>
<note><brief>Prefetch Data Into Caches</brief></note>
</entry>
<entry>
<opcd_ext>1</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>PREFETCHT0</mnem>
<src depend="no"><a>M</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>fetch</grp1>
<note><brief>Prefetch Data Into Caches</brief></note>
</entry>
<entry>
<opcd_ext>2</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>PREFETCHT1</mnem>
<src depend="no"><a>M</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>fetch</grp1>
<note><brief>Prefetch Data Into Caches</brief></note>
</entry>
<entry>
<opcd_ext>3</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>PREFETCHT2</mnem>
<src depend="no"><a>M</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>fetch</grp1>
<note><brief>Prefetch Data Into Caches</brief></note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>4</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>5</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>6</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>7</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<pri_opcd value="19">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<pri_opcd value="1A">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<pri_opcd value="1B">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<pri_opcd value="1C">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<pri_opcd value="1D">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<pri_opcd value="1E">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<!-- 0F1F -->
<pri_opcd value="1F">
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<proc_start>07</proc_start>
<proc_end>08</proc_end>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry>
<opcd_ext>0</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note><brief>No Operation</brief></note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>1</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>2</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>3</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>4</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>5</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>6</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
<entry doc="m" doc_ref="gen_note_hintable_nop_0F18_0F1F">
<opcd_ext>7</opcd_ext>
<proc_start>07</proc_start>
<syntax>
<mnem>HINT_NOP</mnem>
<src depend="no"><a>E</a><t>v</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>control</grp2>
<note>
<brief>Hintable NOP</brief>
</note>
</entry>
</pri_opcd>
<!-- 0F20 -->
<pri_opcd value="20">
<entry r="yes" is_undoc="yes"
doc64_ref="gen_note_MOV_CR_0F20_0F22" ring="0">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>R</a><t>d</t></dst>
<src><a>C</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" particular="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>H</a><t>d</t></dst>
<src><a>C</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
<entry r="yes" is_undoc="yes" ring="0" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>R</a><t>q</t></dst>
<src><a>C</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" mode="e" particular="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>H</a><t>q</t></dst>
<src><a>C</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
</pri_opcd>
<!-- 0F21 -->
<pri_opcd value="21">
<entry r="yes" is_undoc="yes" ring="0">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<!-- 1.02 <dst depend="no"><a>R</a><t>dqp</t></dst>-->
<!-- 1.02 <src><a>D</a><t>dqp</t></src>-->
<dst depend="no"><a>R</a><t>d</t></dst>
<src><a>D</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" particular="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<!-- 1.02 <dst depend="no"><a>H</a><t>dqp</t></dst>-->
<!-- 1.02 <src><a>D</a><t>dqp</t></src>-->
<dst depend="no"><a>H</a><t>d</t></dst>
<src><a>D</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
<entry r="yes" is_undoc="yes" ring="0" mode="e">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>R</a><t>q</t></dst>
<src><a>D</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" mode="e" particular="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>H</a><t>q</t></dst>
<src><a>D</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
</pri_opcd>
<!-- 0F22 -->
<pri_opcd value="22">
<entry r="yes" attr="serial" is_undoc="yes"
doc64_ref="gen_note_MOV_CR_0F20_0F22" ring="0">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>C</a><t>d</t></dst>
<src><a>R</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
<entry r="yes" attr="serial" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" particular="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>C</a><t>d</t></dst>
<src><a>H</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
<entry r="yes" is_undoc="yes" ring="0" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>C</a><t>q</t></dst>
<src><a>R</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" mode="e" particular="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>C</a><t>q</t></dst>
<src><a>H</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Control Registers</brief></note>
</entry>
</pri_opcd>
<!-- 0F23 -->
<pri_opcd value="23">
<entry r="yes" attr="serial" is_undoc="yes" ring="0">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<!-- 1.02 <dst depend="no"><a>D</a><t>dqp</t></dst>-->
<!-- 1.02 <src><a>R</a><t>dqp</t></src>-->
<dst depend="no"><a>D</a><t>d</t></dst>
<src><a>R</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
<entry r="yes" attr="serial" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" particular="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<!-- 1.02 <dst depend="no"><a>D</a><t>dqp</t></dst>-->
<!-- 1.02 <src><a>H</a><t>dqp</t></src>-->
<dst depend="no"><a>D</a><t>q</t></dst>
<src><a>H</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
<entry r="yes" attr="serial" is_undoc="yes" ring="0" mode="e">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>D</a><t>q</t></dst>
<src><a>R</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
<entry r="yes" attr="serial" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" mode="e" particular="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>D</a><t>q</t></dst>
<src><a>H</a><t>q</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Debug Registers</brief></note>
</entry>
</pri_opcd>
<!-- 0F24 -->
<pri_opcd value="24">
<entry r="yes" is_undoc="yes" ring="0">
<proc_start>03</proc_start>
<proc_end>04</proc_end>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>R</a><t>d</t></dst>
<src><a>T</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Test Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" particular="yes">
<proc_start>03</proc_start>
<proc_end>04</proc_end>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>H</a><t>d</t></dst>
<src><a>T</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Test Registers</brief></note>
</entry>
</pri_opcd>
<!-- 0F25: invalid -->
<!-- 0F26 -->
<pri_opcd value="26">
<entry r="yes" is_undoc="yes" ring="0">
<proc_start>03</proc_start>
<proc_end>04</proc_end>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>T</a><t>d</t></dst>
<src><a>R</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Test Registers</brief></note>
</entry>
<entry r="yes" doc="u" is_doc="yes"
doc_ref="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"
ring="0" particular="yes">
<proc_start>03</proc_start>
<proc_end>04</proc_end>
<syntax>
<mnem>MOV</mnem>
<dst depend="no"><a>T</a><t>d</t></dst>
<src><a>H</a><t>d</t></src>
</syntax>
<grp1>system</grp1>
<modif_f>oszapc</modif_f><undef_f>oszapc</undef_f>
<note><brief>Move to/from Test Registers</brief></note>
</entry>
</pri_opcd>
<!-- 0F27: invalid -->
<pri_opcd value="28">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVAPS</mnem>
<dst depend="no"><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Aligned Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVAPD</mnem>
<dst depend="no"><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Aligned Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="29">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVAPS</mnem>
<dst depend="no"><a>W</a><t>ps</t></dst>
<src><a>V</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Move Aligned Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVAPD</mnem>
<dst depend="no"><a>W</a><t>pd</t></dst>
<src><a>V</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Move Aligned Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2A">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>CVTPI2PS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>Q</a><t>pi</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>conver</grp1>
<note><brief>Convert Packed DW Integers to <!--1.11 Packed -->Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>CVTSI2SS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>E</a><t>dqp</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>conver</grp1>
<note><brief>Convert DW Integer to Scalar Single-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTPI2PD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>Q</a><t>pi</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Packed DW Integers to <!--1.11 Packed -->Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTSI2SD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>E</a><t>dqp</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert DW Integer to Scalar Double-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2B">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVNTPS</mnem>
<dst depend="no"><a>M</a><t>ps</t></dst>
<src><a>V</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store Packed Single-FP Values Using Non-Temporal Hint</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVNTPD</mnem>
<dst><a>M</a><t>pd</t></dst>
<src><a>V</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store Packed Double-FP Values Using Non-Temporal Hint</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2C">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>CVTTPS2PI</mnem>
<dst><a>P</a><t>pi</t></dst>
<src><a>W</a><t>psq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>conver</grp1>
<note><brief>Convert with Trunc. Packed Single-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>CVTTSS2SI</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>conver</grp1>
<note><brief>Convert with Trunc. Scalar Single-FP Value to DW Integer</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTTPD2PI</mnem>
<dst><a>P</a><t>pi</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert with Trunc. Packed Double-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTTSD2SI</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Conv. with Trunc. Scalar Double-FP Value to Signed DW Int</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2D">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>CVTPS2PI</mnem>
<dst><a>P</a><t>pi</t></dst>
<src><a>W</a><t>psq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>conver</grp1>
<note><brief>Convert Packed Single-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>CVTSS2SI</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>conver</grp1>
<note><brief>Convert Scalar Single-FP Value to DW Integer</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTPD2PI</mnem>
<dst><a>P</a><t>pi</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Packed Double-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTSD2SI</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Scalar Double-FP Value to DW Integer</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2E">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>UCOMISS</mnem>
<src><a>V</a><t>ss</t></src>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>compar</grp2>
<modif_f>zpc</modif_f><def_f>zpc</def_f>
<note><brief>Unordered Compare Scalar Single-FP Values and Set EFLAGS</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>UCOMISD</mnem>
<src><a>V</a><t>sd</t></src>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>compar</grp2>
<modif_f>zpc</modif_f><def_f>zpc</def_f>
<note><brief>Unordered Compare Scalar Double-FP Values and Set EFLAGS</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="2F">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>COMISS</mnem>
<src><a>V</a><t>ss</t></src>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>compar</grp2>
<modif_f>zpc</modif_f><def_f>zpc</def_f>
<note><brief>Compare Scalar Ordered Single-FP Values and Set EFLAGS</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>COMISD</mnem>
<src><a>V</a><t>sd</t></src>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>compar</grp2>
<modif_f>zpc</modif_f><def_f>zpc</def_f>
<note><brief>Compare Scalar Ordered Double-FP Values and Set EFLAGS</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="30">
<entry attr="serial" ring="0">
<proc_start>05</proc_start>
<syntax>
<mnem>WRMSR</mnem>
<dst group="msr" depend="no" displayed="no">MSR</dst>
<src nr="1" group="gen" type="dqp" displayed="no">rCX</src>
<src nr="0" group="gen" type="dqp" displayed="no">rAX</src>
<src nr="2" group="gen" type="dqp" displayed="no">rDX</src>
</syntax>
<grp1>system</grp1>
<note><brief>Write to Model Specific Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="31">
<entry ring="f" ring_ref="cr4_tsd">
<proc_start>05</proc_start>
<syntax>
<mnem>RDTSC</mnem>
<dst nr="0" group="gen" type="d" depend="no" displayed="no">EAX</dst>
<dst nr="2" group="gen" type="d" depend="no" displayed="no">EDX</dst>
<src nr="10" group="msr" displayed="no">IA32_TIME_STAMP_COUNTER</src>
</syntax>
<grp1>system</grp1>
<note><brief>Read Time-Stamp Counter</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="32">
<entry ring="0">
<proc_start>05</proc_start>
<syntax>
<mnem>RDMSR</mnem>
<dst nr="0" group="gen" type="dqp" depend="no" displayed="no">rAX</dst>
<dst nr="2" group="gen" type="dqp" depend="no" displayed="no">rDX</dst>
<src nr="1" group="gen" type="dqp" displayed="no">rCX</src>
<src group="msr" displayed="no">MSR</src>
</syntax>
<grp1>system</grp1>
<note><brief>Read from Model Specific Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="33">
<entry ring="f" ring_ref="cr4_pce">
<proc_start>06</proc_start>
<syntax>
<mnem>RDPMC</mnem>
<dst nr="0" group="gen" type="d" depend="no" displayed="no">EAX</dst>
<dst nr="2" group="gen" type="d" depend="no" displayed="no">EDX</dst>
<src group="msr" displayed="no">PMC</src>
</syntax>
<grp1>system</grp1>
<note><brief>Read Performance-Monitoring Counters</brief></note>
</entry>
<!-- unnecessary entry
<entry ring="f" ring_ref="cr4_pce" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>RDPMC</mnem>
<dst nr="0" group="gen" type="q" depend="no" displayed="no">RAX</dst>
<dst nr="2" group="gen" type="q" depend="no" displayed="no">RDX</dst>
<src group="msr" displayed="no">PMC</src>
</syntax>
<grp1>system</grp1>
<note><brief>Read Performance-Monitoring Counters</brief></note>
</entry>
-->
</pri_opcd>
<!-- 1.02
<pri_opcd value="34">
<entry doc_ref="gen_note_SYSENTER_0F34" mode="p">
<proc_start>08</proc_start>
<syntax>
<mnem>SYSENTER</mnem>
<src nr="174" group="msr" displayed="no">IA32_SYSENTER_CS</src>
<src nr="175" group="msr" displayed="no">IA32_SYSENTER_ESP</src>
<src nr="176" group="msr" displayed="no">IA32_SYSENTER_EIP</src>
</syntax>
<grp1>system</grp1>
<grp2>branch</grp2>
<grp2>stack</grp2>
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Fast System Call</brief></note>
</entry>
</pri_opcd>
-->
<pri_opcd value="34">
<entry mode="p">
<proc_start>08</proc_start>
<syntax>
<mnem>SYSENTER</mnem>
<dst nr="2" group="seg" type="w" address="S2" displayed="no">SS</dst>
<dst nr="4" group="gen" type="d" displayed="no">ESP</dst>
<src nr="174" group="msr" displayed="no">IA32_SYSENTER_CS</src>
<src nr="175" group="msr" displayed="no">IA32_SYSENTER_ESP</src>
<src nr="176" group="msr" displayed="no">IA32_SYSENTER_EIP</src>
</syntax>
<grp1>system</grp1>
<grp2>branch</grp2>
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Fast System Call</brief></note>
</entry>
<entry doc_ref="gen_note_SYSENTER_0F34" mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>SYSENTER</mnem>
<dst nr="2" group="seg" type="w" address="S2" displayed="no">SS</dst>
<dst nr="4" group="gen" type="q" displayed="no">RSP</dst>
<src nr="174" group="msr" displayed="no">IA32_SYSENTER_CS</src>
<src nr="175" group="msr" displayed="no">IA32_SYSENTER_ESP</src>
<src nr="176" group="msr" displayed="no">IA32_SYSENTER_EIP</src>
</syntax>
<grp1>system</grp1>
<grp2>branch</grp2>
<modif_f>i</modif_f><def_f>i</def_f><f_vals>i</f_vals>
<note><brief>Fast System Call</brief></note>
</entry>
</pri_opcd>
<!-- 1.02
<pri_opcd value="35">
<entry doc64_ref="gen_note_SYSEXIT_0F35" ring="0" mode="p">
<proc_start>08</proc_start>
<syntax>
<mnem>SYSEXIT</mnem>
<src nr="174" group="msr" displayed="no">IA32_SYSENTER_CS</src>
<src nr="1" group="gen" type="dqp" displayed="no">rCX</src>
<src nr="2" group="gen" type="dqp" displayed="no">rDX</src>
</syntax>
<grp1>system</grp1>
<grp2>branch</grp2>
<grp2>stack</grp2>
<grp3>trans</grp3>
<note><brief>Fast Return from Fast System Call</brief></note>
</entry>
</pri_opcd>
-->
<pri_opcd value="35">
<entry doc64_ref="gen_note_SYSEXIT_0F35" ring="0" mode="p">
<proc_start>08</proc_start>
<syntax>
<mnem>SYSEXIT</mnem>
<dst nr="2" group="seg" type="w" address="S2" displayed="no">SS</dst>
<dst nr="4" group="gen" type="dqp" displayed="no">eSP</dst>
<src nr="174" group="msr" displayed="no">IA32_SYSENTER_CS</src>
<src nr="1" group="gen" type="dqp" displayed="no">rCX</src>
<src nr="2" group="gen" type="dqp" displayed="no">rDX</src>
</syntax>
<grp1>system</grp1>
<grp2>branch</grp2>
<grp3>trans</grp3>
<note><brief>Fast Return from Fast System Call</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="37">
<!-- note: some of them work also in real-address mode -->
<!-- note: some of them don't require ring 0 -->
<entry doc_ref="gen_note_GETSEC_0F37">
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>GETSEC</mnem>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
</syntax>
<instr_ext>smx</instr_ext>
<note>
<brief>GETSEC Leaf Functions</brief>
</note>
</entry>
</pri_opcd>
<!-- 0F38: 3-byte escape -->
<pri_opcd value="38">
<!-- 0F38 00 -->
<entry r="yes">
<sec_opcd escape="yes">00</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSHUFB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Shuffle Bytes</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">00</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSHUFB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Shuffle Bytes</brief></note>
</entry>
<!-- 0F38 01 -->
<entry r="yes">
<sec_opcd escape="yes">01</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHADDW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Add</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">01</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHADDW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Add</brief></note>
</entry>
<!-- 0F38 02 -->
<entry r="yes">
<sec_opcd escape="yes">02</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHADDD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Add</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">02</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHADDD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Add</brief></note>
</entry>
<!-- 0F38 03 -->
<entry r="yes">
<sec_opcd escape="yes">03</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHADDSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Add and Saturate</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">03</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHADDSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Add and Saturate</brief></note>
</entry>
<!-- 0F38 04 -->
<entry r="yes">
<sec_opcd escape="yes">04</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PMADDUBSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Multiply and Add Packed Signed and Unsigned Bytes</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">04</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PMADDUBSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Multiply and Add Packed Signed and Unsigned Bytes</brief></note>
</entry>
<!-- 0F38 05 -->
<entry r="yes">
<sec_opcd escape="yes">05</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHSUBW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Subtract</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">05</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHSUBW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Subtract</brief></note>
</entry>
<!-- 0F38 06 -->
<entry r="yes">
<sec_opcd escape="yes">06</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHSUBD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Subtract</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">06</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHSUBD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Subtract</brief></note>
</entry>
<!-- 0F38 07 -->
<entry r="yes">
<sec_opcd escape="yes">07</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHSUBSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Subtract and Saturate</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">07</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PHSUBSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Horizontal Subtract and Saturate</brief></note>
</entry>
<!-- 0F38 08 -->
<entry r="yes">
<sec_opcd escape="yes">08</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSIGNB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed SIGN</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">08</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSIGNB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed SIGN</brief></note>
</entry>
<!-- 0F38 09 -->
<entry r="yes">
<sec_opcd escape="yes">09</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSIGNW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed SIGN</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">09</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSIGNW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed SIGN</brief></note>
</entry>
<!-- 0F38 0A -->
<entry r="yes">
<sec_opcd escape="yes">0A</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSIGND</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed SIGN</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">0A</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PSIGND</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed SIGN</brief></note>
</entry>
<!-- 0F38 0B -->
<entry r="yes">
<sec_opcd escape="yes">0B</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PMULHRSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Multiply High with Round and Scale</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">0B</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PMULHRSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Multiply High with Round and Scale</brief></note>
</entry>
<!-- 0F38 10 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">10</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PBLENDVB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Variable Blend Packed Bytes</brief>
</note>
</entry>
<!-- 0F38 14 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">14</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>BLENDVPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Variable Blend Packed Single-FP Values</brief>
</note>
</entry>
<!-- 0F38 15 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">15</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>BLENDVPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Variable Blend Packed Double-FP Values</brief>
</note>
</entry>
<!-- 0F38 17 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">17</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PTEST</mnem>
<src><a>V</a><t>dq</t></src>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<f_vals>osap</f_vals>
<note>
<brief>Logical Compare</brief>
</note>
</entry>
<!-- 0F38 1C -->
<entry r="yes">
<sec_opcd escape="yes">1C</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PABSB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Absolute Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">1C</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PABSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Absolute Value</brief></note>
</entry>
<!-- 0F38 1D -->
<entry r="yes">
<sec_opcd escape="yes">1D</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PABSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Absolute Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">1D</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PABSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Absolute Value</brief></note>
</entry>
<!-- 0F38 1E -->
<entry r="yes">
<sec_opcd escape="yes">1E</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PABSD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Absolute Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">1E</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PABSD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Absolute Value</brief></note>
</entry>
<!-- 0F38 20 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">20</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVSXBW</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVSXBW</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Sign Extend</brief>
</note>
</entry>
<!-- 0F38 21 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">21</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVSXBD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>d</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVSXBD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Sign Extend</brief>
</note>
</entry>
<!-- 0F38 22 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">22</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVSXBQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>w</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVSXBQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Sign Extend</brief>
</note>
</entry>
<!-- 0F38 23 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">23</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVSXWD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVSXWD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Sign Extend</brief>
</note>
</entry>
<!-- 0F38 24 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">24</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVSXWQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>d</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVSXWQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Sign Extend</brief>
</note>
</entry>
<!-- 0F38 25 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">25</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVSXDQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVSXDQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Sign Extend</brief>
</note>
</entry>
<!-- 0F38 28 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">28</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMULDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note>
<brief>Multiply Packed Signed Dword Integers</brief>
</note>
</entry>
<!-- 0F38 29 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">29</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PCMPEQQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Compare Packed Qword Data for Equal</brief>
</note>
</entry>
<!-- 0F38 2A -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">2A</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>MOVNTDQA</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>M</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>cachect</grp1>
<note>
<brief>Load Double Quadword Non-Temporal Aligned Hint</brief>
</note>
</entry>
<!-- 0F38 2B -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">2B</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PACKUSDW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Pack with Unsigned Saturation</brief>
</note>
</entry>
<!-- 0F38 30 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">30</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVZXBW</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVZXBW</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Zero Extend</brief>
</note>
</entry>
<!-- 0F38 31 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">31</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVZXBD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>d</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVZXBD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Zero Extend</brief>
</note>
</entry>
<!-- 0F38 32 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">32</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVZXBQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>w</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVZXBQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Zero Extend</brief>
</note>
</entry>
<!-- 0F38 33 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">33</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVZXWD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVZXWD</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Zero Extend</brief>
</note>
</entry>
<!-- 0F38 34 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">34</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVZXWQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>d</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVZXWQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Zero Extend</brief>
</note>
</entry>
<!-- 0F38 35 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">35</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PMOVZXDQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>q</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PMOVZXDQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note>
<brief>Packed Move with Zero Extend</brief>
</note>
</entry>
<!-- 0F38 37 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">37</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PCMPGTQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse42</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Compare Packed Qword Data for Greater Than</brief>
<det>Compare packed qwords in xmm2/m128 and xmm1 for greater than</det>
</note>
</entry>
<!-- 0F38 38 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">38</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMINSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Minimum of Packed Signed Byte Integers</brief>
</note>
</entry>
<!-- 0F38 39 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">39</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMINSD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Minimum of Packed Signed Dword Integers</brief>
</note>
</entry>
<!-- 0F38 3A -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">3A</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMINUW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Minimum of Packed Unsigned Word Integers</brief>
</note>
</entry>
<!-- 0F38 3B -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">3B</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMINUD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Minimum of Packed Unsigned Dword Integers</brief>
</note>
</entry>
<!-- 0F38 3C -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">3C</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMAXSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Maximum of Packed Signed Byte Integers</brief>
</note>
</entry>
<!-- 0F38 3D -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">3D</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMAXSD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Maximum of Packed Signed Dword Integers</brief>
</note>
</entry>
<!-- 0F38 3E -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">3E</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMAXUW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Maximum of Packed Unsigned Word Integers</brief>
</note>
</entry>
<!-- 0F38 3F -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">3F</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMAXUD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Maximum of Packed Unsigned Dword Integers</brief>
</note>
</entry>
<!-- 0F38 40 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">40</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PMULLD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note>
<brief>Multiply Packed Signed Dword Integers and Store Low Result</brief>
</note>
</entry>
<!-- 0F38 41 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">41</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PHMINPOSUW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note>
<brief>Packed Horizontal Word Minimum</brief>
</note>
</entry>
<!-- 0F38 80 -->
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<pref>66</pref>
<sec_opcd escape="yes">80</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>INVEPT</mnem>
<src><a>G</a><t>d</t></src>
<src><a>M</a><t>dq</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Invalidate Translations Derived from EPT</brief>
<det>Invalidates EPT-derived entries in the TLBs and paging-structure caches</det>
</note>
</entry>
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="e">
<pref>66</pref>
<sec_opcd escape="yes">80</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>INVEPT</mnem>
<src><a>G</a><t>q</t></src>
<src><a>M</a><t>dq</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Invalidate Translations Derived from EPT</brief>
<det>Invalidates EPT-derived entries in the TLBs and paging-structure caches</det>
</note>
</entry>
<!-- 0F38 81 -->
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<pref>66</pref>
<sec_opcd escape="yes">81</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>INVVPID</mnem>
<src><a>G</a><t>d</t></src>
<src><a>M</a><t>dq</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Invalidate Translations Based on VPID</brief>
<det>Invalidates entries in the TLBs and paging-structure caches based on VPID</det>
</note>
</entry>
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="e">
<pref>66</pref>
<sec_opcd escape="yes">81</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>INVVPID</mnem>
<src><a>G</a><t>q</t></src>
<src><a>M</a><t>dq</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Invalidate Translations Based on VPID</brief>
<det>Invalidates entries in the TLBs and paging-structure caches based on VPID</det>
</note>
</entry>
<!-- 0F38 F0 -->
<entry r="yes">
<sec_opcd escape="yes">F0</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>MOVBE</mnem>
<dst><a>G</a><t>vqp</t></dst>
<src><a>M</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2>
<note>
<brief>Move Data After Swapping Bytes</brief>
<det>Reverse byte order in op2 and move to op1</det>
</note>
</entry>
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>F2</pref>
<sec_opcd escape="yes">F0</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>CRC32</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>E</a><t>b</t></src>
</syntax>
<instr_ext>sse42</instr_ext>
<note>
<brief>Accumulate CRC32 Value</brief>
<det>Accumulate CRC32 on r/m8</det>
</note>
</entry>
<!-- 0F38 F1 -->
<entry r="yes">
<sec_opcd escape="yes">F1</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>MOVBE</mnem>
<dst><a>M</a><t>vqp</t></dst>
<src><a>G</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2>
<note>
<brief>Move Data After Swapping Bytes</brief>
<det>Reverse byte order in op2 and move to op1</det>
</note>
</entry>
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>F2</pref>
<sec_opcd escape="yes">F1</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>CRC32</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>E</a><t>vqp</t></src>
</syntax>
<instr_ext>sse42</instr_ext>
<note>
<brief>Accumulate CRC32 Value</brief>
<det>Accumulate CRC32 on r/m8</det>
</note>
</entry>
</pri_opcd>
<!-- 0F3A: 3-byte escape -->
<pri_opcd value="3A">
<!-- 0F3A 08 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">08</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>ROUNDPS</mnem>
<dst depend="no"><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>conver</grp2>
<note><brief>Round Packed Single-FP Values</brief></note>
</entry>
<!-- 0F3A 09 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">09</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>ROUNDPD</mnem>
<dst depend="no"><a>V</a><t>ps</t></dst>
<src><a>W</a><t>pd</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>conver</grp2>
<note><brief>Round Packed Double-FP Values</brief></note>
</entry>
<!-- 0F3A 0A -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">0A</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>ROUNDSS</mnem>
<dst depend="no"><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>conver</grp2>
<note><brief>Round Scalar Single-FP Values</brief></note>
</entry>
<!-- 0F3A 0B -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">0B</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>ROUNDSD</mnem>
<dst depend="no"><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>conver</grp2>
<note><brief>Round Scalar Double-FP Values</brief></note>
</entry>
<!-- 0F3A 0C -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">0C</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>BLENDPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note>
<brief>Blend Packed Single-FP Values</brief>
</note>
</entry>
<!-- 0F3A 0D -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">0D</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>BLENDPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note>
<brief>Blend Packed Double-FP Values</brief>
</note>
</entry>
<!-- 0F3A 0E -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">0E</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PBLENDW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Blend Packed Words</brief>
</note>
</entry>
<!-- 0F3A 0F -->
<entry r="yes">
<sec_opcd escape="yes">0F</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PALIGNR</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Align Right</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<sec_opcd escape="yes">0F</sec_opcd>
<proc_start>12</proc_start>
<syntax>
<mnem>PALIGNR</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>ssse3</instr_ext>
<grp1>simdint</grp1>
<note><brief>Packed Align Right</brief></note>
</entry>
<!-- 0F3A 14 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">14</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PEXTRB</mnem>
<dst><a>M</a><t>b</t></dst>
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PEXTRB</mnem>
<dst><a>R</a><t>dqp</t></dst>
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Extract Byte</brief>
</note>
</entry>
<!-- 0F3A 15 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">15</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>PEXTRW</mnem>
<dst><a>M</a><t>w</t></dst>
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax mod="nomem">
<mnem>PEXTRW</mnem>
<dst><a>R</a><t>dqp</t></dst>
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Extract Word</brief>
</note>
</entry>
<!-- 0F3A 16 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">16</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PEXTRD</mnem>
<dst><a>E</a><t>d</t></dst> <!-- note: "do" type can't be used here -->
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax>
<mnem>PEXTRQ</mnem>
<dst><a>E</a><t>qp</t></dst>
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note>
<brief>Extract Dword/Qword</brief>
</note>
</entry>
<!-- 0F3A 17 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">17</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<!-- EXTRACTPS uses single Ed syntax instead of
two separate Md and Rdqp because the 'dqp' type is not
neccessary here; however, it is a bit questionable if this
100% follows ideal Intel syntax (which doesn't exist at the
time of adding this instruction -->
<syntax>
<mnem>EXTRACTPS</mnem>
<dst><a>E</a><t>d</t></dst>
<src><a>V</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note>
<brief>Extract Packed Single-FP Value</brief>
</note>
</entry>
<!-- 0F3A 20 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">20</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="nomem">
<mnem>PINSRB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>M</a><t>b</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<!-- to keep the syntax of SSE zero-extending instructions
consistent, Rdqp must be used instead of just Rd -->
<syntax mod="mem">
<mnem>PINSRB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>R</a><t>dqp</t></src> <!-- effective type is 'b' -->
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Insert Byte</brief></note>
</entry>
<!-- 0F3A 21 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">21</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax mod="mem">
<mnem>INSERTPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>U</a><t>ps</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax mod="nomem">
<mnem>INSERTPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>M</a><t>d</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note>
<brief>Insert Packed Single-FP Value</brief>
</note>
</entry>
<!-- 0F3A 22 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">22</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PINSRD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>E</a><t>d</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax>
<mnem>PINSRQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>E</a><t>qp</t></src> <!-- effective type is 'b' -->
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Insert Dword/Qword</brief></note>
</entry>
<!-- 0F3A 40 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">40</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>DPPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note>
<brief>Dot Product of Packed Single-FP Values</brief>
</note>
</entry>
<!-- 0F3A 41 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">41</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>DPPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note>
<brief>Dot Product of Packed Double-FP Values</brief>
</note>
</entry>
<!-- 0F3A 42 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">42</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>MPSADBW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse41</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note>
<brief>Compute Multiple Packed Sums of Absolute Difference</brief>
</note>
</entry>
<!-- 0F3A 60 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">60</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PCMPESTRM</mnem>
<dst nr="0" group="xmm" displayed="no">XMM0</dst>
<src><a>V</a><t>dq</t></src>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
<src nr="0" group="gen" type="dqp" displayed="no">rAX</src>
<src nr="2" group="gen" type="dqp" displayed="no">rDX</src>
</syntax>
<instr_ext>sse42</instr_ext>
<grp1>strtxt</grp1>
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<f_vals>ap</f_vals>
<note>
<brief>Packed Compare Explicit Length Strings, Return Mask</brief>
<det>Perform a packed comparison of string data with
explicit lengths, generating a mask, and storing the result
in XMM0</det>
</note>
</entry>
<!-- 0F3A 61 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">61</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PCMPESTRI</mnem>
<dst nr="1" group="gen" type="dqp" displayed="no">rCX</dst>
<src><a>V</a><t>dq</t></src>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
<src nr="0" group="gen" type="dqp" displayed="no">rAX</src>
<src nr="2" group="gen" type="dqp" displayed="no">rDX</src>
</syntax>
<instr_ext>sse42</instr_ext>
<grp1>strtxt</grp1>
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<f_vals>ap</f_vals>
<note>
<brief>Packed Compare Explicit Length Strings, Return Index</brief>
<det>Perform a packed comparison of string data with
explicit lengths, generating an index, and storing the
result in rCX</det>
</note>
</entry>
<!-- 0F3A 62 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">62</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PCMPISTRM</mnem>
<dst nr="0" group="xmm" displayed="no">XMM0</dst>
<src><a>V</a><t>dq</t></src>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse42</instr_ext>
<grp1>strtxt</grp1>
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<f_vals>ap</f_vals>
<note>
<brief>Packed Compare Implicit Length Strings, Return Mask</brief>
<det>Perform a packed comparison of string data with
implicit lengths, generating a mask, and storing the result
in XMM0</det>
</note>
</entry>
<!-- 0F3A 63 -->
<entry r="yes" doc_ref="gen_note_SSE4_amd">
<pref>66</pref>
<sec_opcd escape="yes">63</sec_opcd>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>PCMPISTRI</mnem>
<dst nr="1" group="gen" type="dqp" displayed="no">rCX</dst>
<src><a>V</a><t>dq</t></src>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse42</instr_ext>
<grp1>strtxt</grp1>
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<f_vals>ap</f_vals>
<note>
<brief>Packed Compare Implicit Length Strings, Return Index</brief>
<det>Perform a packed comparison of string data with
implicit lengths, generating an index, and storing the
result in rCX</det>
</note>
</entry>
</pri_opcd>
<!-- 0F40 -->
<pri_opcd value="40">
<entry tttn="0000" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVO</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>o</test_f>
<note><brief>Conditional Move - overflow (OF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="41">
<entry tttn="0001" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNO</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>o</test_f>
<note><brief>Conditional Move - not overflow (OF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="42">
<entry tttn="0010" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVB</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVNAE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVC</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<note><brief>Conditional Move - below/not above or equal/carry (CF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="43">
<entry tttn="0011" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNB</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVAE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVNC</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<note><brief>Conditional Move - not below/above or equal/not carry (CF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="44">
<entry tttn="0100" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVZ</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<note><brief>Conditional Move - zero/equal (ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="45">
<entry tttn="0101" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNZ</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVNE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<note><brief>Conditional Move - not zero/not equal (ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="46">
<entry tttn="0110" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVBE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVNA</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Conditional Move - below or equal/not above (CF=1 AND ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="47">
<entry tttn="0111" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNBE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVA</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Conditional Move - not below or equal/above (CF=0 AND ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="48">
<entry tttn="1000" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVS</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>s</test_f>
<note><brief>Conditional Move - sign (SF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="49">
<entry tttn="1001" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNS</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>s</test_f>
<note><brief>Conditional Move - not sign (SF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4A">
<entry tttn="1010" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVP</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVPE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>p</test_f>
<note><brief>Conditional Move - parity/parity even (PF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4B">
<entry tttn="1011" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNP</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVPO</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>p</test_f>
<note><brief>Conditional Move - not parity/parity odd</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4C">
<entry tttn="1100" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVL</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVNGE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>os</test_f>
<note><brief>Conditional Move - less/not greater (SF!=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4D">
<entry tttn="1101" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNL</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVGE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>os</test_f>
<note><brief>Conditional Move - not less/greater or equal (SF=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4E">
<entry tttn="1110" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVLE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVNG</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>osz</test_f>
<note><brief>Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="4F">
<entry tttn="1111" r="yes" doc64_ref="gen_note_CMOVcc_0F40-0F4F">
<proc_start>07</proc_start>
<syntax><mnem>CMOVNLE</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<syntax><mnem>CMOVG</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>osz</test_f>
<note><brief>Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="50">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVMSKPS</mnem>
<dst><a>G</a><t>dqp</t></dst> <!-- only four low-order bits are rewritten -->
<src><a>U</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>datamov</grp2>
<note><brief>Extract Packed Single-FP Sign Mask</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVMSKPD</mnem>
<dst><a>G</a><t>dqp</t></dst> <!-- only two low-order bits are rewritten -->
<src><a>U</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>datamov</grp2>
<note><brief>Extract Packed Double-FP Sign Mask</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="51">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>SQRTPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Compute Square Roots of Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>SQRTSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Compute Square Root of Scalar Single-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>SQRTPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Compute Square Roots of Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>SQRTSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Compute Square Root of Scalar Double-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="52">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>RSQRTPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Compute Recipr. of Square Roots of Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>RSQRTSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Compute Recipr. of Square Root of Scalar Single-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="53">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>RCPPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Compute Reciprocals of Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>RCPSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Compute Reciprocal of Scalar Single-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="54">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>ANDPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical AND of Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>ANDPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical AND of Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="55">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>ANDNPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical AND NOT of Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>ANDNPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical AND NOT of Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="56">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>ORPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical OR of Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>ORPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical OR of Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="57">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>XORPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical XOR for Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>XORPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical XOR for Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="58">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>ADDPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>ADDSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Add Scalar Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>ADDPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>ADDSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Add Scalar Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="59">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MULPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>MULSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Scalar Single-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MULPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MULSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Scalar Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="5A">
<entry r="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>CVTPS2PD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Packed Single-FP Values to <!--1.11 Packed -->Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTPD2PS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Packed Double-FP Values to <!--1.11 Packed -->Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTSS2SD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Scalar Single-FP Value to Scalar Double-FP Value </brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTSD2SS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Scalar Double-FP Value to Scalar Single-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="5B">
<entry r="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>CVTDQ2PS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksp</grp1>
<note><brief>Convert Packed DW Integers to <!--1.11 Packed -->Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTPS2DQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksp</grp1>
<note><brief>Convert Packed Single-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTTPS2DQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksp</grp1>
<note><brief>Convert with Trunc. Packed Single-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="5C">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>SUBPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>SUBSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Scalar Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>SUBPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>SUBSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Scalar Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="5D">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MINPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Return Minimum Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>MINSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Return Minimum Scalar Single-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MINPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Return Minimum Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MINSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Return Minimum Scalar Double-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="5E">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>DIVPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Divide Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>DIVSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Divide Scalar Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>DIVPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Divide Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>DIVSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Divide Scalar Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="5F">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MAXPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Return Maximum Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>MAXSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Return Maximum Scalar Single-FP Value</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MAXPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Return Maximum Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MAXSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>arith</grp2>
<note><brief>Return Maximum Scalar Double-FP Value</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="60">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PUNPCKLBW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>unpack</grp1>
<note><brief>Unpack Low Data</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKLBW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack Low Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="61">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PUNPCKLWD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>unpack</grp1>
<note><brief>Unpack Low Data</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKLWD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack Low Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="62">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PUNPCKLDQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>unpack</grp1>
<note><brief>Unpack Low Data</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKLDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack Low Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="63">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PACKSSWB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>conver</grp1>
<note><brief>Pack with Signed Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PACKSSWB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note><brief>Pack with Signed Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="64">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PCMPGTB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>compar</grp1>
<note><brief>Compare Packed Signed Integers for Greater Than</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PCMPGTB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Signed Integers for Greater Than</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="65">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PCMPGTW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>compar</grp1>
<note><brief>Compare Packed Signed Integers for Greater Than</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PCMPGTW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Signed Integers for Greater Than</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="66">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PCMPGTD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>compar</grp1>
<note><brief>Compare Packed Signed Integers for Greater Than</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PCMPGTD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Signed Integers for Greater Than</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="67">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PACKUSWB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>conver</grp1>
<note><brief>Pack with Unsigned Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PACKUSWB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note><brief>Pack with Unsigned Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="68">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PUNPCKHBW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>unpack</grp1>
<note><brief>Unpack High Data</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKHBW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack High Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="69">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PUNPCKHWD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>unpack</grp1>
<note><brief>Unpack High Data</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKHWD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack High Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6A">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PUNPCKHDQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>unpack</grp1>
<note><brief>Unpack High Data</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKHDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack High Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6B">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PACKSSDW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>conver</grp1>
<note><brief>Pack with Signed Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PACKSSDW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>conver</grp2>
<note><brief>Pack with Signed Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6C">
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKLQDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack Low Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6D">
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PUNPCKHQDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Unpack High Data</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6E">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst><a>P</a><t>q</t></dst> <!-- can't depend="no" -->
<src><a>E</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>datamov</grp1>
<note><brief>Move Doubleword</brief></note>
</entry>
<entry r="yes" doc64_ref="gen_note_MOVQ_0F6E_660F6E_0F7E_660F7E"
mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst><a>P</a><t>q</t></dst> <!-- can't depend="no" -->
<src><a>E</a><t>d</t></src> <!-- note: "do" type can't be used here -->
</syntax>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>P</a><t>q</t></dst>
<src><a>E</a><t>qp</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>datamov</grp1>
<note><brief>Move Doubleword/Quadword</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst><a>V</a><t>dq</t></dst> <!-- can't depend="no" -->
<src><a>E</a><t>d</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Doubleword</brief></note>
</entry>
<entry r="yes" doc64_ref="gen_note_MOVQ_0F6E_660F6E_0F7E_660F7E"
mode="e">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst><a>V</a><t>dq</t></dst> <!-- can't depend="no" -->
<src><a>E</a><t>d</t></src> <!-- note: "do" type can't be used here -->
</syntax>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>E</a><t>qp</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Doubleword/Quadword</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="6F">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>datamov</grp1>
<note><brief>Move Quadword</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVDQA</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Aligned Double Quadword</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVDQU</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Unaligned Double Quadword</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="70">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PSHUFW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Shuffle Packed Words</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSHUFLW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Shuffle Packed Low Words</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSHUFHW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Shuffle Packed High Words</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSHUFD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shunpck</grp2>
<note><brief>Shuffle Packed Doublewords</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="71">
<entry>
<opcd_ext>2</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSRLW</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<entry>
<opcd_ext>2</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLW</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<entry>
<opcd_ext>4</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSRAW</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
<entry>
<opcd_ext>4</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRAW</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSLLW</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLW</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="72">
<entry>
<opcd_ext>2</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSRLD</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Double Quadword Right Logical</brief></note>
</entry>
<entry>
<opcd_ext>2</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLD</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Double Quadword Right Logical</brief></note>
</entry>
<entry>
<opcd_ext>4</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSRAD</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
<entry>
<opcd_ext>4</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRAD</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSLLD</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLD</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="73">
<entry>
<opcd_ext>2</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSRLQ</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<entry>
<opcd_ext>2</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLQ</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry>
<opcd_ext>3</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLDQ</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Double Quadword Right Logical</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<proc_start>06</proc_start>
<syntax>
<mnem>PSLLQ</mnem>
<dst><a>N</a><t>q</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLQ</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<!--<entry mod="nomem">-->
<entry>
<opcd_ext>7</opcd_ext>
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLDQ</mnem>
<dst><a>U</a><t>dq</t></dst>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Double Quadword Left Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="74">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PCMPEQB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>compar</grp1>
<note><brief>Compare Packed Data for Equal</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PCMPEQB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Data for Equal</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="75">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PCMPEQW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>compar</grp1>
<note><brief>Compare Packed Data for Equal</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PCMPEQW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Data for Equal</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="76">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PCMPEQD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>compar</grp1>
<note><brief>Compare Packed Data for Equal</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PCMPEQD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Data for Equal</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="77">
<entry>
<proc_start>06</proc_start>
<syntax>
<mnem>EMMS</mnem>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>x87fpu</grp1>
<grp2>control</grp2>
<note><brief>Empty MMX Technology State</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="78">
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMREAD</mnem>
<dst><a>E</a><t>d</t></dst>
<src><a>G</a><t>d</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Read Field from Virtual-Machine Control Structure</brief>
<det>Reads a specified VMCS field</det>
</note>
</entry>
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="e">
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMREAD</mnem>
<dst><a>E</a><t>q</t></dst>
<src><a>G</a><t>q</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Read Field from Virtual-Machine Control Structure</brief>
<det>Reads a specified VMCS field</det>
</note>
</entry>
</pri_opcd>
<pri_opcd value="79">
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMWRITE</mnem>
<src><a>G</a><t>d</t></src>
<src><a>E</a><t>d</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Write Field to Virtual-Machine Control Structure</brief>
<det>Writes a specified VMCS field</det>
</note>
</entry>
<entry r="yes" doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="e">
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMWRITE</mnem>
<src><a>G</a><t>q</t></src>
<src><a>E</a><t>q</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Write Field to Virtual-Machine Control Structure</brief>
<det>Writes a specified VMCS field</det>
</note>
</entry>
</pri_opcd>
<!-- 0F7A-0F7B: invalid opcodes -->
<pri_opcd value="7C">
<entry r="yes">
<pref>66</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>HADDPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Packed Double-FP Horizontal Add</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>HADDPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Packed Single-FP Horizontal Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7D">
<entry r="yes">
<pref>66</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>HSUBPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Packed Double-FP Horizontal Subtract</brief></note>
</entry>
<entry r="yes">
<!-- 1.02 <pref>66</pref>-->
<pref>F2</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>HSUBPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Packed Single-FP Horizontal Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7E">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst depend="no"><a>E</a><t>d</t></dst>
<src><a>P</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>datamov</grp1>
<note><brief>Move Doubleword</brief></note>
</entry>
<entry r="yes" doc64_ref="gen_note_MOVQ_0F6E_660F6E_0F7E_660F7E"
mode="e">
<proc_start>10</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst depend="no"><a>E</a><t>d</t></dst> <!-- note: "do" type can't be used here -->
<src><a>P</a><t>q</t></src>
</syntax>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>E</a><t>qp</t></dst>
<src><a>P</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>datamov</grp1>
<note><brief>Move Doubleword/Quadword</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst depend="no"><a>E</a><t>d</t></dst>
<src><a>V</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Doubleword</brief></note>
</entry>
<entry r="yes" doc64_ref="gen_note_MOVQ_0F6E_660F6E_0F7E_660F7E"
mode="e">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVD</mnem>
<dst depend="no"><a>E</a><t>d</t></dst> <!-- note: "do" type can't be used here -->
<src><a>V</a><t>dq</t></src>
</syntax>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>E</a><t>qp</t></dst>
<src><a>E</a><t>dq </t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Doubleword/Quadword</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>V</a><t>q</t></dst>
<src><a>W</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Quadword</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="7F">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>MOVQ</mnem>
<dst depend="no"><a>Q</a><t>q</t></dst>
<src><a>P</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>datamov</grp1>
<note><brief>Move Quadword</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVDQA</mnem>
<dst depend="no"><a>W</a><t>dq</t></dst>
<src><a>V</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Aligned Double Quadword</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVDQU</mnem>
<dst depend="no"><a>W</a><t>dq</t></dst>
<src><a>V</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Unaligned Double Quadword</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="80">
<entry tttn="0000" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JO</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>o</test_f>
<note><brief>Jump short if overflow (OF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="81">
<entry tttn="0001" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNO</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>o</test_f>
<note><brief>Jump short if not overflow (OF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="82">
<entry tttn="0010" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JB</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JNAE</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JC</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>c</test_f>
<note><brief>Jump short if below/not above or equal/carry (CF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="83">
<entry tttn="0011" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNB</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JAE</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JNC</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>c</test_f>
<note><brief>Jump short if not below/above or equal/not carry (CF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="84">
<entry tttn="0100" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JZ</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JE</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Jump short if zero/equal (ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="85">
<entry tttn="0101" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNZ</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JNE</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>z</test_f>
<note><brief>Jump short if not zero/not equal (ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="86">
<entry tttn="0110" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JBE</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JNA</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Jump short if below or equal/not above (CF=1 AND ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="87">
<entry tttn="0111" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNBE</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JA</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Jump short if not below or equal/above (CF=0 AND ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="88">
<entry tttn="1000" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JS</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>s</test_f>
<note><brief>Jump short if sign (SF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="89">
<entry tttn="1001" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNS</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>s</test_f>
<note><brief>Jump short if not sign (SF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8A">
<entry tttn="1010" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JP</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JPE</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>p</test_f>
<note><brief>Jump short if parity/parity even (PF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8B">
<entry tttn="1011" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNP</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JPO</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>p</test_f>
<note><brief>Jump short if not parity/parity odd</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8C">
<entry tttn="1100" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JL</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JNGE</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>os</test_f>
<note><brief>Jump short if less/not greater (SF!=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8D">
<entry tttn="1101" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNL</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JGE</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>os</test_f>
<note><brief>Jump short if not less/greater or equal (SF=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8E">
<entry tttn="1110" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JLE</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JNG</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>osz</test_f>
<note><brief>Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="8F">
<entry tttn="1111" doc64_ref="gen_note_short_near_jmp">
<proc_start>03</proc_start>
<syntax><mnem>JNLE</mnem><src><a>J</a><t>vds</t></src></syntax>
<syntax><mnem>JG</mnem><src><a>J</a><t>vds</t></src></syntax>
<grp1>gen</grp1><grp2>branch</grp2><grp3>cond</grp3>
<test_f>osz</test_f>
<note><brief>Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="90">
<entry tttn="0000" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETO</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>o</test_f>
<note><brief>Set Byte on Condition - overflow (OF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="91">
<entry tttn="0001" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNO</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>o</test_f>
<note><brief>Set Byte on Condition - not overflow (OF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="92">
<entry tttn="0010" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETB</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETNAE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETC</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<note><brief>Set Byte on Condition - below/not above or equal/carry (CF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="93">
<entry tttn="0011" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNB</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETAE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETNC</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>c</test_f>
<note><brief>Set Byte on Condition - not below/above or equal/not carry (CF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="94">
<entry tttn="0100" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETZ</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<note><brief>Set Byte on Condition - zero/equal (ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="95">
<entry tttn="0101" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNZ</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETNE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>z</test_f>
<note><brief>Set Byte on Condition - not zero/not equal (ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="96">
<entry tttn="0110" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETBE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETNA</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="97">
<entry tttn="0111" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNBE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETA</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<!-- 1.02 <test_f>cz</test_f>-->
<test_f>zc</test_f>
<note><brief>Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="98">
<entry tttn="1000" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETS</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>s</test_f>
<note><brief>Set Byte on Condition - sign (SF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="99">
<entry tttn="1001" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNS</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>s</test_f>
<note><brief>Set Byte on Condition - not sign (SF=0)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9A">
<entry tttn="1010" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETP</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETPE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>p</test_f>
<note><brief>Set Byte on Condition - parity/parity even (PF=1)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9B">
<entry tttn="1011" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNP</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETPO</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>p</test_f>
<note><brief>Set Byte on Condition - not parity/parity odd</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9C">
<entry tttn="1100" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETL</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETNGE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>os</test_f>
<note><brief>Set Byte on Condition - less/not greater (SF!=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9D">
<entry tttn="1101" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNL</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETGE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>os</test_f>
<note><brief>Set Byte on Condition - not less/greater or equal (SF=OF)</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9E">
<entry tttn="1110" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETLE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETNG</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>osz</test_f>
<note><brief>Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="9F">
<entry tttn="1111" doc_ref="gen_note_SETcc_0F90-0F9F">
<opcd_ext>0</opcd_ext>
<proc_start>03</proc_start>
<syntax><mnem>SETNLE</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<syntax><mnem>SETG</mnem><dst depend="no"><a>E</a><t>b</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<test_f>osz</test_f>
<note><brief>Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A0">
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="4" group="seg" type="w" address="S33">FS</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A1">
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>POP</mnem>
<dst nr="4" group="seg" type="w" address="S33" depend="no">FS</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A2">
<entry attr="serial">
<proc_start lat_step="yes">04</proc_start>
<syntax>
<mnem>CPUID</mnem>
<dst nr="8B" group="msr" depend="no" displayed="no">IA32_BIOS_SIGN_ID</dst>
<dst nr="0" group="gen" type="d" displayed="no">EAX</dst>
<dst nr="1" group="gen" type="d" depend="no" displayed="no">ECX</dst>
<dst nr="2" group="gen" type="d" depend="no" displayed="no">EDX</dst>
<dst nr="3" group="gen" type="d" depend="no" displayed="no">EBX</dst>
</syntax>
<grp1>gen</grp1><grp2>control</grp2>
<note><brief>CPU Identification</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A3">
<entry r="yes">
<proc_start>03</proc_start>
<syntax><mnem>BT</mnem><src><a>E</a><t>vqp</t></src><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A4">
<entry direction="0" r="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>SHLD</mnem>
<dst><a>E</a><t>vqp</t></dst>
<src><a>G</a><t>vqp</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Double Precision Shift Left</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A5">
<entry direction="0" r="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>SHLD</mnem>
<dst><a>E</a><t>vqp</t></dst>
<src><a>G</a><t>vqp</t></src>
<src nr="1" group="gen" type="b">CL</src>
</syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Double Precision Shift Left</brief></note>
</entry>
</pri_opcd>
<!-- 0FA6-0FA7: invalid -->
<pri_opcd value="A8">
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>PUSH</mnem>
<dst address="SC" displayed="no">SS:[rSP]</dst> <!-- 1.02 -->
<src nr="5" group="seg" type="w" address="S33">GS</src>
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Push Word, Doubleword or Quadword Onto the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="A9">
<entry>
<proc_start>03</proc_start>
<syntax>
<mnem>POP</mnem>
<dst nr="5" group="seg" type="w" address="S33" depend="no">GS</dst>
<src address="SC" displayed="no">SS:[rSP]</src> <!-- 1.02 -->
</syntax>
<grp1>gen</grp1><grp2>stack</grp2><grp2>segreg</grp2>
<note><brief>Pop a Value from the Stack</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AA">
<entry mode="s" particular="yes">
<proc_start lat_step="yes">03</proc_start>
<syntax>
<mnem>RSM</mnem>
<dst type="w" address="F" depend="no" displayed="no">Flags</dst>
</syntax>
<grp1>system</grp1><grp2>branch</grp2>
<!-- 1.10 <modif_f>odiszapc</modif_f><def_f>odiszapc</def_f>-->
<note><brief>Resume from System Management Mode</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AB">
<entry r="yes" lock="yes">
<proc_start>03</proc_start>
<syntax><mnem>BTS</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test and Set</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AC">
<entry direction="0" r="yes">
<proc_start>03</proc_start>
<syntax><mnem>SHRD</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Double Precision Shift Right</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AD">
<entry direction="0" r="yes">
<proc_start>03</proc_start>
<syntax>
<mnem>SHRD</mnem>
<dst><a>E</a><t>vqp</t></dst>
<src><a>G</a><t>vqp</t></src>
<src nr="1" group="gen" type="b">CL</src>
</syntax>
<grp1>gen</grp1><grp2>shftrot</grp2>
<modif_f>oszapc</modif_f><def_f>oszpc</def_f><undef_f>oac</undef_f>
<note><brief>Double Precision Shift Right</brief></note>
</entry>
</pri_opcd>
<!-- 0FAE -->
<pri_opcd value="AE">
<!--<entry mod="mem">-->
<entry>
<opcd_ext>0</opcd_ext>
<proc_start lat_step="yes">08</proc_start>
<syntax>
<mnem>FXSAVE</mnem>
<dst depend="no"><a>M</a><t>stx</t></dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
<src nr="2" group="x87fpu" displayed="no">ST2</src>
<src nr="3" group="x87fpu" displayed="no">ST3</src>
<src nr="4" group="x87fpu" displayed="no">ST4</src>
<src nr="5" group="x87fpu" displayed="no">ST5</src>
<src nr="6" group="x87fpu" displayed="no">ST6</src>
<src nr="7" group="x87fpu" displayed="no">ST7</src>
<src nr="0" group="mmx" displayed="no">MMX0</src>
<src nr="1" group="mmx" displayed="no">MMX1</src>
<src nr="2" group="mmx" displayed="no">MMX2</src>
<src nr="3" group="mmx" displayed="no">MMX3</src>
<src nr="4" group="mmx" displayed="no">MMX4</src>
<src nr="5" group="mmx" displayed="no">MMX5</src>
<src nr="6" group="mmx" displayed="no">MMX6</src>
<src nr="7" group="mmx" displayed="no">MMX7</src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
<src nr="1" group="xmm" displayed="no">XMM1</src>
<src nr="2" group="xmm" displayed="no">XMM2</src>
<src nr="3" group="xmm" displayed="no">XMM3</src>
<src nr="4" group="xmm" displayed="no">XMM4</src>
<src nr="5" group="xmm" displayed="no">XMM5</src>
<src nr="6" group="xmm" displayed="no">XMM6</src>
<src nr="7" group="xmm" displayed="no">XMM7</src>
</syntax>
<grp1>sm</grp1>
<note><brief>Save x87 FPU, MMX, XMM, and MXCSR State</brief></note>
</entry>
<!--<entry mod="mem" mode="e">-->
<entry mode="e">
<opcd_ext>0</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>FXSAVE</mnem>
<dst depend="no"><a>M</a><t>stx</t></dst>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
<src nr="2" group="x87fpu" displayed="no">ST2</src>
<src nr="3" group="x87fpu" displayed="no">ST3</src>
<src nr="4" group="x87fpu" displayed="no">ST4</src>
<src nr="5" group="x87fpu" displayed="no">ST5</src>
<src nr="6" group="x87fpu" displayed="no">ST6</src>
<src nr="7" group="x87fpu" displayed="no">ST7</src>
<src nr="0" group="mmx" displayed="no">MMX0</src>
<src nr="1" group="mmx" displayed="no">MMX1</src>
<src nr="2" group="mmx" displayed="no">MMX2</src>
<src nr="3" group="mmx" displayed="no">MMX3</src>
<src nr="4" group="mmx" displayed="no">MMX4</src>
<src nr="5" group="mmx" displayed="no">MMX5</src>
<src nr="6" group="mmx" displayed="no">MMX6</src>
<src nr="7" group="mmx" displayed="no">MMX7</src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
<src nr="1" group="xmm" displayed="no">XMM1</src>
<src nr="2" group="xmm" displayed="no">XMM2</src>
<src nr="3" group="xmm" displayed="no">XMM3</src>
<src nr="4" group="xmm" displayed="no">XMM4</src>
<src nr="5" group="xmm" displayed="no">XMM5</src>
<src nr="6" group="xmm" displayed="no">XMM6</src>
<src nr="7" group="xmm" displayed="no">XMM7</src>
<src nr="8" group="xmm" displayed="no">XMM8</src>
<src nr="9" group="xmm" displayed="no">XMM9</src>
<src nr="10" group="xmm" displayed="no">XMM10</src>
<src nr="11" group="xmm" displayed="no">XMM11</src>
<src nr="12" group="xmm" displayed="no">XMM12</src>
<src nr="13" group="xmm" displayed="no">XMM13</src>
<src nr="14" group="xmm" displayed="no">XMM14</src>
<src nr="15" group="xmm" displayed="no">XMM15</src>
</syntax>
<grp1>sm</grp1>
<note><brief>Save x87 FPU, MMX, XMM, and MXCSR State</brief></note>
</entry>
<!--<entry mod="mem">-->
<entry>
<opcd_ext>1</opcd_ext>
<proc_start lat_step="yes">08</proc_start>
<syntax>
<mnem>FXRSTOR</mnem>
<dst nr="0" group="x87fpu" depend="no" displayed="no">ST</dst>
<dst nr="1" group="x87fpu" depend="no" displayed="no">ST1</dst>
<dst nr="2" group="x87fpu" depend="no" displayed="no">ST2</dst>
<dst nr="3" group="x87fpu" depend="no" displayed="no">ST3</dst>
<dst nr="4" group="x87fpu" depend="no" displayed="no">ST4</dst>
<dst nr="5" group="x87fpu" depend="no" displayed="no">ST5</dst>
<dst nr="6" group="x87fpu" depend="no" displayed="no">ST6</dst>
<dst nr="7" group="x87fpu" depend="no" displayed="no">ST7</dst>
<dst nr="0" group="mmx" depend="no" displayed="no">MMX0</dst>
<dst nr="1" group="mmx" depend="no" displayed="no">MMX1</dst>
<dst nr="2" group="mmx" depend="no" displayed="no">MMX2</dst>
<dst nr="3" group="mmx" depend="no" displayed="no">MMX3</dst>
<dst nr="4" group="mmx" depend="no" displayed="no">MMX4</dst>
<dst nr="5" group="mmx" depend="no" displayed="no">MMX5</dst>
<dst nr="6" group="mmx" depend="no" displayed="no">MMX6</dst>
<dst nr="7" group="mmx" depend="no" displayed="no">MMX7</dst>
<dst nr="0" group="xmm" depend="no" displayed="no">XMM0</dst>
<dst nr="1" group="xmm" depend="no" displayed="no">XMM1</dst>
<dst nr="2" group="xmm" depend="no" displayed="no">XMM2</dst>
<dst nr="3" group="xmm" depend="no" displayed="no">XMM3</dst>
<dst nr="4" group="xmm" depend="no" displayed="no">XMM4</dst>
<dst nr="5" group="xmm" depend="no" displayed="no">XMM5</dst>
<dst nr="6" group="xmm" depend="no" displayed="no">XMM6</dst>
<dst nr="7" group="xmm" depend="no" displayed="no">XMM7</dst>
<src><a>M</a><t>stx</t></src>
</syntax>
<grp1>sm</grp1>
<note><brief>Restore x87 FPU, MMX, XMM, and MXCSR State</brief></note>
</entry>
<!--<entry mod="mem" mode="e">-->
<entry mode="e">
<opcd_ext>1</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>FXRSTOR</mnem>
<dst nr="0" group="x87fpu" depend="no" displayed="no">ST</dst>
<dst nr="1" group="x87fpu" depend="no" displayed="no">ST1</dst>
<dst nr="2" group="x87fpu" depend="no" displayed="no">ST2</dst>
<dst nr="3" group="x87fpu" depend="no" displayed="no">ST3</dst>
<dst nr="4" group="x87fpu" depend="no" displayed="no">ST4</dst>
<dst nr="5" group="x87fpu" depend="no" displayed="no">ST5</dst>
<dst nr="6" group="x87fpu" depend="no" displayed="no">ST6</dst>
<dst nr="7" group="x87fpu" depend="no" displayed="no">ST7</dst>
<dst nr="0" group="mmx" depend="no" displayed="no">MMX0</dst>
<dst nr="1" group="mmx" depend="no" displayed="no">MMX1</dst>
<dst nr="2" group="mmx" depend="no" displayed="no">MMX2</dst>
<dst nr="3" group="mmx" depend="no" displayed="no">MMX3</dst>
<dst nr="4" group="mmx" depend="no" displayed="no">MMX4</dst>
<dst nr="5" group="mmx" depend="no" displayed="no">MMX5</dst>
<dst nr="6" group="mmx" depend="no" displayed="no">MMX6</dst>
<dst nr="7" group="mmx" depend="no" displayed="no">MMX7</dst>
<dst nr="0" group="xmm" depend="no" displayed="no">XMM0</dst>
<dst nr="1" group="xmm" depend="no" displayed="no">XMM1</dst>
<dst nr="2" group="xmm" depend="no" displayed="no">XMM2</dst>
<dst nr="3" group="xmm" depend="no" displayed="no">XMM3</dst>
<dst nr="4" group="xmm" depend="no" displayed="no">XMM4</dst>
<dst nr="5" group="xmm" depend="no" displayed="no">XMM5</dst>
<dst nr="6" group="xmm" depend="no" displayed="no">XMM6</dst>
<dst nr="7" group="xmm" depend="no" displayed="no">XMM7</dst>
<dst nr="8" group="xmm" depend="no" displayed="no">XMM8</dst>
<dst nr="9" group="xmm" depend="no" displayed="no">XMM9</dst>
<dst nr="10" group="xmm" depend="no" displayed="no">XMM10</dst>
<dst nr="11" group="xmm" depend="no" displayed="no">XMM11</dst>
<dst nr="12" group="xmm" depend="no" displayed="no">XMM12</dst>
<dst nr="13" group="xmm" depend="no" displayed="no">XMM13</dst>
<dst nr="14" group="xmm" depend="no" displayed="no">XMM14</dst>
<dst nr="15" group="xmm" depend="no" displayed="no">XMM15</dst>
<src><a>M</a><t>stx</t></src>
</syntax>
<grp1>sm</grp1>
<note><brief>Restore x87 FPU, MMX, XMM, and MXCSR State</brief></note>
</entry>
<entry>
<opcd_ext>2</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>LDMXCSR</mnem>
<src><a>M</a><t>d</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>mxcsrsm</grp1>
<note><brief>Load MXCSR Register</brief></note>
</entry>
<entry>
<opcd_ext>3</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>STMXCSR</mnem>
<dst><a>M</a><t>d</t></dst>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>mxcsrsm</grp1>
<note><brief>Store MXCSR Register State</brief></note>
</entry>
<entry>
<opcd_ext>4</opcd_ext>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<!-- for now, XSAVE supports only those registers supported by FXSAVE -->
<mnem>XSAVE</mnem>
<dst><a>M</a></dst>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
<src nr="2" group="x87fpu" displayed="no">ST2</src>
<src nr="3" group="x87fpu" displayed="no">ST3</src>
<src nr="4" group="x87fpu" displayed="no">ST4</src>
<src nr="5" group="x87fpu" displayed="no">ST5</src>
<src nr="6" group="x87fpu" displayed="no">ST6</src>
<src nr="7" group="x87fpu" displayed="no">ST7</src>
<src nr="0" group="mmx" displayed="no">MMX0</src>
<src nr="1" group="mmx" displayed="no">MMX1</src>
<src nr="2" group="mmx" displayed="no">MMX2</src>
<src nr="3" group="mmx" displayed="no">MMX3</src>
<src nr="4" group="mmx" displayed="no">MMX4</src>
<src nr="5" group="mmx" displayed="no">MMX5</src>
<src nr="6" group="mmx" displayed="no">MMX6</src>
<src nr="7" group="mmx" displayed="no">MMX7</src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
<src nr="1" group="xmm" displayed="no">XMM1</src>
<src nr="2" group="xmm" displayed="no">XMM2</src>
<src nr="3" group="xmm" displayed="no">XMM3</src>
<src nr="4" group="xmm" displayed="no">XMM4</src>
<src nr="5" group="xmm" displayed="no">XMM5</src>
<src nr="6" group="xmm" displayed="no">XMM6</src>
<src nr="7" group="xmm" displayed="no">XMM7</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Save Processor Extended States</brief>
<det>Save processor extended states to memory. The states are specified by EDX:EAX</det>
</note>
</entry>
<entry mode="e">
<opcd_ext>4</opcd_ext>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<!-- for now, XSAVE supports only those registers supported by FXSAVE -->
<mnem>XSAVE</mnem>
<dst><a>M</a></dst>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
<src nr="0" group="x87fpu" displayed="no">ST</src>
<src nr="1" group="x87fpu" displayed="no">ST1</src>
<src nr="2" group="x87fpu" displayed="no">ST2</src>
<src nr="3" group="x87fpu" displayed="no">ST3</src>
<src nr="4" group="x87fpu" displayed="no">ST4</src>
<src nr="5" group="x87fpu" displayed="no">ST5</src>
<src nr="6" group="x87fpu" displayed="no">ST6</src>
<src nr="7" group="x87fpu" displayed="no">ST7</src>
<src nr="0" group="mmx" displayed="no">MMX0</src>
<src nr="1" group="mmx" displayed="no">MMX1</src>
<src nr="2" group="mmx" displayed="no">MMX2</src>
<src nr="3" group="mmx" displayed="no">MMX3</src>
<src nr="4" group="mmx" displayed="no">MMX4</src>
<src nr="5" group="mmx" displayed="no">MMX5</src>
<src nr="6" group="mmx" displayed="no">MMX6</src>
<src nr="7" group="mmx" displayed="no">MMX7</src>
<src nr="0" group="xmm" displayed="no">XMM0</src>
<src nr="1" group="xmm" displayed="no">XMM1</src>
<src nr="2" group="xmm" displayed="no">XMM2</src>
<src nr="3" group="xmm" displayed="no">XMM3</src>
<src nr="4" group="xmm" displayed="no">XMM4</src>
<src nr="5" group="xmm" displayed="no">XMM5</src>
<src nr="6" group="xmm" displayed="no">XMM6</src>
<src nr="7" group="xmm" displayed="no">XMM7</src>
<src nr="8" group="xmm" displayed="no">XMM8</src>
<src nr="9" group="xmm" displayed="no">XMM9</src>
<src nr="10" group="xmm" displayed="no">XMM10</src>
<src nr="11" group="xmm" displayed="no">XMM11</src>
<src nr="12" group="xmm" displayed="no">XMM12</src>
<src nr="13" group="xmm" displayed="no">XMM13</src>
<src nr="14" group="xmm" displayed="no">XMM14</src>
<src nr="15" group="xmm" displayed="no">XMM15</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Save Processor Extended States</brief>
<det>Save processor extended states to memory. The states are specified by EDX:EAX</det>
</note>
</entry>
<entry mod="nomem">
<opcd_ext>5</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>LFENCE</mnem>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>order</grp1>
<note><brief>Load Fence</brief></note>
</entry>
<entry mod="mem">
<opcd_ext>5</opcd_ext>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<!-- for now, XRSTOR supports only those registers supported by FXRSTOR -->
<mnem>XRSTOR</mnem>
<dst nr="0" group="x87fpu" depend="no" displayed="no">ST</dst>
<dst nr="1" group="x87fpu" depend="no" displayed="no">ST1</dst>
<dst nr="2" group="x87fpu" depend="no" displayed="no">ST2</dst>
<dst nr="3" group="x87fpu" depend="no" displayed="no">ST3</dst>
<dst nr="4" group="x87fpu" depend="no" displayed="no">ST4</dst>
<dst nr="5" group="x87fpu" depend="no" displayed="no">ST5</dst>
<dst nr="6" group="x87fpu" depend="no" displayed="no">ST6</dst>
<dst nr="7" group="x87fpu" depend="no" displayed="no">ST7</dst>
<dst nr="0" group="mmx" depend="no" displayed="no">MMX0</dst>
<dst nr="1" group="mmx" depend="no" displayed="no">MMX1</dst>
<dst nr="2" group="mmx" depend="no" displayed="no">MMX2</dst>
<dst nr="3" group="mmx" depend="no" displayed="no">MMX3</dst>
<dst nr="4" group="mmx" depend="no" displayed="no">MMX4</dst>
<dst nr="5" group="mmx" depend="no" displayed="no">MMX5</dst>
<dst nr="6" group="mmx" depend="no" displayed="no">MMX6</dst>
<dst nr="7" group="mmx" depend="no" displayed="no">MMX7</dst>
<dst nr="0" group="xmm" depend="no" displayed="no">XMM0</dst>
<dst nr="1" group="xmm" depend="no" displayed="no">XMM1</dst>
<dst nr="2" group="xmm" depend="no" displayed="no">XMM2</dst>
<dst nr="3" group="xmm" depend="no" displayed="no">XMM3</dst>
<dst nr="4" group="xmm" depend="no" displayed="no">XMM4</dst>
<dst nr="5" group="xmm" depend="no" displayed="no">XMM5</dst>
<dst nr="6" group="xmm" depend="no" displayed="no">XMM6</dst>
<dst nr="7" group="xmm" depend="no" displayed="no">XMM7</dst>
<src><a>M</a></src>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Restore Processor Extended States</brief>
<det>Restore processor extended states from memory. The states are specified by EDX:EAX</det>
</note>
</entry>
<entry mod="mem" mode="e">
<opcd_ext>5</opcd_ext>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<!-- for now, XRSTOR supports only those registers supported by FXRSTOR -->
<mnem>XRSTOR</mnem>
<dst nr="0" group="x87fpu" depend="no" displayed="no">ST</dst>
<dst nr="1" group="x87fpu" depend="no" displayed="no">ST1</dst>
<dst nr="2" group="x87fpu" depend="no" displayed="no">ST2</dst>
<dst nr="3" group="x87fpu" depend="no" displayed="no">ST3</dst>
<dst nr="4" group="x87fpu" depend="no" displayed="no">ST4</dst>
<dst nr="5" group="x87fpu" depend="no" displayed="no">ST5</dst>
<dst nr="6" group="x87fpu" depend="no" displayed="no">ST6</dst>
<dst nr="7" group="x87fpu" depend="no" displayed="no">ST7</dst>
<dst nr="0" group="mmx" depend="no" displayed="no">MMX0</dst>
<dst nr="1" group="mmx" depend="no" displayed="no">MMX1</dst>
<dst nr="2" group="mmx" depend="no" displayed="no">MMX2</dst>
<dst nr="3" group="mmx" depend="no" displayed="no">MMX3</dst>
<dst nr="4" group="mmx" depend="no" displayed="no">MMX4</dst>
<dst nr="5" group="mmx" depend="no" displayed="no">MMX5</dst>
<dst nr="6" group="mmx" depend="no" displayed="no">MMX6</dst>
<dst nr="7" group="mmx" depend="no" displayed="no">MMX7</dst>
<dst nr="0" group="xmm" depend="no" displayed="no">XMM0</dst>
<dst nr="1" group="xmm" depend="no" displayed="no">XMM1</dst>
<dst nr="2" group="xmm" depend="no" displayed="no">XMM2</dst>
<dst nr="3" group="xmm" depend="no" displayed="no">XMM3</dst>
<dst nr="4" group="xmm" depend="no" displayed="no">XMM4</dst>
<dst nr="5" group="xmm" depend="no" displayed="no">XMM5</dst>
<dst nr="6" group="xmm" depend="no" displayed="no">XMM6</dst>
<dst nr="7" group="xmm" depend="no" displayed="no">XMM7</dst>
<dst nr="8" group="xmm" depend="no" displayed="no">XMM8</dst>
<dst nr="9" group="xmm" depend="no" displayed="no">XMM9</dst>
<dst nr="10" group="xmm" depend="no" displayed="no">XMM10</dst>
<dst nr="11" group="xmm" depend="no" displayed="no">XMM11</dst>
<dst nr="12" group="xmm" depend="no" displayed="no">XMM12</dst>
<dst nr="13" group="xmm" depend="no" displayed="no">XMM13</dst>
<dst nr="14" group="xmm" depend="no" displayed="no">XMM14</dst>
<dst nr="15" group="xmm" depend="no" displayed="no">XMM15</dst>
<src><a>M</a></src>
<src nr="2" group="gen" type="d" displayed="no">EDX</src>
<src nr="0" group="gen" type="d" displayed="no">EAX</src>
</syntax>
<grp1>system</grp1>
<note>
<brief>Restore Processor Extended States</brief>
<det>Restore processor extended states from memory. The states are specified by EDX:EAX</det>
</note>
</entry>
<entry>
<opcd_ext>6</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>MFENCE</mnem>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>order</grp1>
<note><brief>Memory Fence</brief></note>
</entry>
<entry mod="nomem">
<opcd_ext>7</opcd_ext>
<proc_start>09</proc_start>
<syntax>
<mnem>SFENCE</mnem>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>order</grp1>
<note><brief>Store Fence</brief></note>
</entry>
<entry mod="mem">
<opcd_ext>7</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>CLFLUSH</mnem>
<src depend="no"><a>M</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>cachect</grp1>
<note><brief>Flush Cache Line</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="AF">
<entry direction="1" op_size="1" r="yes">
<proc_start>03</proc_start>
<syntax><mnem>IMUL</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oc</def_f><undef_f>szap</undef_f>
<note><brief>Signed Multiply</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B0">
<entry direction="0" op_size="0" r="yes" lock="yes"
doc_ref="gen_note_CMPXCHG_0FB0_0FB1">
<proc_start>04</proc_start>
<syntax>
<mnem>CMPXCHG</mnem>
<dst><a>E</a><t>b</t></dst>
<dst nr="0" group="gen" type="b" displayed="no">AL</dst>
<src><a>G</a><t>b</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2>
<grp2>arith</grp2>
<grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare and Exchange</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B1">
<entry direction="0" op_size="1" r="yes" lock="yes"
doc_ref="gen_note_CMPXCHG_0FB0_0FB1">
<proc_start>04</proc_start>
<syntax>
<mnem>CMPXCHG</mnem>
<dst><a>E</a><t>vqp</t></dst>
<dst nr="0" group="gen" type="vqp" displayed="no">rAX</dst>
<src><a>G</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2>
<grp2>arith</grp2>
<grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Compare and Exchange</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B2">
<entry r="yes" doc64_ref="gen_note_LSS_0FB2_LFS_0FB4_LGS_0FB5">
<proc_start>03</proc_start>
<syntax>
<mnem>LSS</mnem>
<dst nr="2" group="seg" type="w" address="S30" displayed="no">SS</dst>
<dst><a>G</a><t>vqp</t></dst>
<src><a>M</a><t>ptp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>segreg</grp2>
<note><brief>Load Far Pointer</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B3">
<entry r="yes" lock="yes">
<proc_start>03</proc_start>
<syntax><mnem>BTR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test and Reset</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B4">
<!--<entry r="yes" mod="mem" doc64_ref="gen_note_LSS_0FB2_LFS_0FB4_LGS_0FB5">-->
<entry r="yes" doc64_ref="gen_note_LSS_0FB2_LFS_0FB4_LGS_0FB5">
<proc_start>03</proc_start>
<syntax>
<mnem>LFS</mnem>
<dst nr="4" group="seg" type="w" address="S30" displayed="no">FS</dst>
<dst><a>G</a><t>vqp</t></dst>
<src><a>M</a><t>ptp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>segreg</grp2>
<note><brief>Load Far Pointer</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B5">
<!--<entry r="yes" mod="mem" doc64_ref="gen_note_LSS_0FB2_LFS_0FB4_LGS_0FB5">-->
<entry r="yes" doc64_ref="gen_note_LSS_0FB2_LFS_0FB4_LGS_0FB5">
<proc_start>03</proc_start>
<syntax>
<mnem>LGS</mnem>
<dst nr="5" group="seg" type="w" address="S30" displayed="no">GS</dst>
<dst><a>G</a><t>vqp</t></dst>
<src><a>M</a><t>ptp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>segreg</grp2>
<note><brief>Load Far Pointer</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B6">
<entry direction="1" op_size="0" r="yes">
<proc_start>03</proc_start>
<syntax><mnem>MOVZX</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Move with Zero-Extend</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B7">
<entry direction="1" op_size="1" r="yes">
<proc_start>03</proc_start>
<syntax><mnem>MOVZX</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>w</t></src></syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Move with Zero-Extend</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="B8">
<entry>
<proc_start>99</proc_start>
<syntax><mnem>JMPE</mnem></syntax>
<grp1>system</grp1><grp2>branch</grp2>
<note><brief>Jump to IA-64 Instruction Set</brief></note>
</entry>
<entry r="yes"> <!-- note: POPCNT is not a part of SSE4 -->
<pref>F3</pref>
<proc_start lat_step="yes">12</proc_start>
<syntax>
<mnem>POPCNT</mnem>
<dst><a>G</a><t>vqp</t></dst>
<src><a>E</a><t>vqp</t></src>
</syntax>
<grp1>gen</grp1>
<grp2>bit</grp2>
<modif_f>oszapc</modif_f>
<f_vals>osapc</f_vals>
<note>
<brief>Bit Population Count</brief>
<det>Count the 1s in op2</det>
</note>
</entry>
</pri_opcd>
<pri_opcd value="B9">
<entry r="yes" attr="invd" doc="m"
doc_ref="gen_note_sug_UD_0FB9"> <!-- r=yes fixed in 1.02 -->
<proc_start>02</proc_start>
<syntax>
<mnem sug="yes">UD</mnem>
<src depend="no"><a>G</a></src>
<src depend="no"><a>E</a></src>
</syntax>
<grp1>gen</grp1><grp2>control</grp2>
<note><brief>Undefined Instruction</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="BA">
<proc_start>03</proc_start>
<entry>
<opcd_ext>4</opcd_ext>
<syntax><mnem>BT</mnem><src><a>E</a><t>vqp</t></src><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test</brief></note>
</entry>
<entry lock="yes">
<opcd_ext>5</opcd_ext>
<syntax><mnem>BTS</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test and Set</brief></note>
</entry>
<entry lock="yes">
<opcd_ext>6</opcd_ext>
<syntax><mnem>BTR</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test and Reset</brief></note>
</entry>
<entry lock="yes">
<opcd_ext>7</opcd_ext>
<syntax><mnem>BTC</mnem><dst><a>E</a><t>vqp</t></dst><src><a>I</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test and Complement</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="BB">
<entry r="yes" lock="yes">
<proc_start>03</proc_start>
<syntax><mnem>BTC</mnem><dst><a>E</a><t>vqp</t></dst><src><a>G</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>c</def_f><undef_f>oszap</undef_f>
<note><brief>Bit Test and Complement</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="BC">
<entry r="yes" doc64_ref="gen_note_BSF_0FBC_BSR_0FBD">
<proc_start>03</proc_start>
<syntax><mnem>BSF</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>z</def_f><undef_f>osapc</undef_f>
<note><brief>Bit Scan Forward</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="BD">
<entry r="yes" doc64_ref="gen_note_BSF_0FBC_BSR_0FBD">
<proc_start>03</proc_start>
<syntax><mnem>BSR</mnem><dst><a>G</a><t>vqp</t></dst><src><a>E</a><t>vqp</t></src></syntax>
<grp1>gen</grp1><grp2>bit</grp2>
<modif_f>oszapc</modif_f><def_f>z</def_f><undef_f>osapc</undef_f>
<note><brief>Bit Scan Reverse</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="BE">
<entry direction="1" op_size="0" r="yes">
<proc_start>03</proc_start>
<syntax><mnem>MOVSX</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>b</t></src></syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Move with Sign-Extension</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="BF">
<entry direction="1" op_size="1" r="yes">
<proc_start>03</proc_start>
<syntax><mnem>MOVSX</mnem><dst depend="no"><a>G</a><t>vqp</t></dst><src><a>E</a><t>w</t></src></syntax>
<grp1>gen</grp1><grp2>conver</grp2>
<note><brief>Move with Sign-Extension</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C0">
<entry direction="0" op_size="0" r="yes" lock="yes">
<proc_start>04</proc_start>
<syntax><mnem>XADD</mnem><dst><a>E</a><t>b</t></dst><dst><a>G</a><t>b</t></dst></syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>arith</grp2>
<grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Exchange and Add</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="C1">
<entry direction="0" op_size="1" r="yes" lock="yes">
<proc_start>04</proc_start>
<syntax><mnem>XADD</mnem><dst><a>E</a><t>vqp</t></dst><dst><a>G</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>arith</grp2>
<grp3>binary</grp3>
<modif_f>oszapc</modif_f><def_f>oszapc</def_f>
<note><brief>Exchange and Add</brief></note>
</entry>
</pri_opcd>
<!-- 0FC2 -->
<pri_opcd value="C2">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>CMPPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>CMPSS</mnem>
<dst><a>V</a><t>ss</t></dst>
<src><a>W</a><t>ss</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>compar</grp2>
<note><brief>Compare Scalar Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CMPPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>compar</grp2>
<note><brief>Compare Packed Double-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CMPSD</mnem>
<dst><a>V</a><t>sd</t></dst>
<src><a>W</a><t>sd</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>compar</grp2>
<note><brief>Compare Scalar Double-FP Values</brief></note>
</entry>
</pri_opcd>
<!-- 0FC3 -->
<pri_opcd value="C3">
<entry r="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>MOVNTI</mnem>
<dst depend="no"><a>M</a><t>dqp</t></dst>
<src><a>G</a><t>dqp</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store Doubleword Using Non-Temporal Hint</brief></note>
</entry>
</pri_opcd>
<!-- 0FC4 -->
<pri_opcd value="C4">
<entry r="yes">
<proc_start>09</proc_start>
<syntax mod="nomem">
<mnem>PINSRW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>R</a><t>dqp</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax mod="mem">
<mnem>PINSRW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>M</a><t>w</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<!-- past 1.02 <grp2>compar</grp2>-->
<note><brief>Insert Word</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax mod="nomem">
<mnem>PINSRW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>R</a><t>dqp</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<syntax mod="mem">
<mnem>PINSRW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>M</a><t>w</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<!-- past 1.02 <grp2>word</grp2>-->
<note><brief>Insert Word</brief></note>
</entry>
</pri_opcd>
<!-- 0FC5 -->
<pri_opcd value="C5">
<!--<entry r="yes" mod="nomem">-->
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PEXTRW</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>N</a><t>q</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<!-- past 1.02 <grp2>word</grp2>-->
<note><brief>Extract Word</brief></note>
</entry>
<!--<entry r="yes" mod="nomem">-->
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PEXTRW</mnem>
<dst><a>G</a><t>dqp</t></dst>
<src><a>U</a><t>dq</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<!-- past 1.02 <grp2>word</grp2>-->
<note><brief>Extract Word</brief></note>
</entry>
</pri_opcd>
<!-- 0FC6 -->
<pri_opcd value="C6">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>SHUFPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdfp</grp1>
<grp2>shunpck</grp2>
<note><brief>Shuffle Packed Single-FP Values</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>SHUFPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
<src><a>I</a><t>b</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>shunpck</grp2>
<note><brief>Shuffle Packed Double-FP Values</brief></note>
</entry>
</pri_opcd>
<!-- 0FC7 -->
<pri_opcd value="C7">
<entry lock="yes" doc_ref="gen_note_CMPXCHG8B_CMPXCHG16B_0FC7_1">
<opcd_ext>1</opcd_ext>
<proc_start>05</proc_start>
<syntax>
<mnem>CMPXCHG8B</mnem>
<dst><a>M</a><t>q</t></dst>
<dst nr="0" group="gen" type="d" displayed="no">EAX</dst>
<dst nr="2" group="gen" type="d" displayed="no">EDX</dst>
<src nr="3" group="gen" type="d" displayed="no">EBX</src>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>arith</grp2>
<grp3>binary</grp3>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Compare and Exchange Bytes</brief></note>
</entry>
<entry lock="yes" doc64_ref="gen_note_CMPXCHG8B_CMPXCHG16B_0FC7_1" mode="e">
<opcd_ext>1</opcd_ext>
<proc_start>10</proc_start>
<syntax>
<mnem>CMPXCHG8B</mnem>
<dst><a>M</a><t>q</t></dst>
<!-- note: "do" type can't be used here -->
<dst nr="0" group="gen" type="d" displayed="no">EAX</dst>
<dst nr="2" group="gen" type="d" displayed="no">EDX</dst>
<src nr="3" group="gen" type="d" displayed="no">EBX</src>
<src nr="1" group="gen" type="d" displayed="no">ECX</src>
</syntax>
<syntax>
<mnem>CMPXCHG16B</mnem>
<dst><a>M</a><t>dq</t></dst>
<dst nr="0" group="gen" type="qp" displayed="no">RAX</dst>
<dst nr="2" group="gen" type="qp" displayed="no">RDX</dst>
<src nr="3" group="gen" type="qp" displayed="no">RBX</src>
<src nr="1" group="gen" type="qp" displayed="no">RCX</src>
</syntax>
<grp1>gen</grp1>
<grp2>datamov</grp2><grp2>arith</grp2><grp3>binary</grp3>
<modif_f>z</modif_f><def_f>z</def_f>
<note><brief>Compare and Exchange Bytes</brief></note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<opcd_ext>6</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMPTRLD</mnem>
<src><a>M</a><t>q</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Load Pointer to Virtual-Machine Control Structure</brief>
<det>Loads the current VMCS pointer from memory</det>
</note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<pref>66</pref>
<opcd_ext>6</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMCLEAR</mnem>
<dst><a>M</a><t>q</t></dst>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Clear Virtual-Machine Control Structure</brief>
<det>Copy VMCS data to VMCS region in memory</det>
</note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<pref>F3</pref>
<opcd_ext>6</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMXON</mnem>
<src><a>M</a><t>q</t></src>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Enter VMX Operation</brief>
<det>Enter VMX root operation</det>
</note>
</entry>
<entry doc_ref="gen_note_VMX_vs_SVM" ring="0" mode="p">
<opcd_ext>7</opcd_ext>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>VMPTRST</mnem>
<dst><a>M</a><t>q</t></dst>
</syntax>
<instr_ext>vmx</instr_ext>
<!-- <grp1>system</grp1>-->
<modif_f>oszapc</modif_f>
<def_f>oszapc</def_f>
<note>
<brief>Store Pointer to Virtual-Machine Control Structure</brief>
<det>Stores the current VMCS pointer into memory</det>
</note>
</entry>
</pri_opcd>
<pri_opcd value="C8">
<entry doc_ref="gen_note_BSWAP_0FC8">
<proc_start>04</proc_start>
<syntax><mnem>BSWAP</mnem><dst><a>Z</a><t>vqp</t></dst></syntax>
<grp1>gen</grp1><grp2>datamov</grp2>
<note><brief>Byte Swap</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D0">
<entry r="yes">
<pref>66</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>ADDSUBPD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Packed Double-FP Add/Subtract</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>ADDSUBPS</mnem>
<dst><a>V</a><t>ps</t></dst>
<src><a>W</a><t>ps</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>simdfp</grp1>
<grp2>arith</grp2>
<note><brief>Packed Single-FP Add/Subtract</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D1">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSRLW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D2">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSRLD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D3">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSRLQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRLQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Right Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D4">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Quadword Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Quadword Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D5">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PMULLW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Multiply Packed Signed Integers and Store Low Result</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PMULLW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Packed Signed Integers and Store Low Result</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D6">
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVQ</mnem>
<dst><a>W</a><t>q</t></dst> <!-- can't depend="no" -->
<src><a>V</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Quadword</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVQ2DQ</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>N</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Quadword from MMX Technology to XMM Register</brief></note>
</entry>
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVDQ2Q</mnem>
<dst depend="no"><a>P</a><t>q</t></dst>
<src><a>U</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>datamov</grp2>
<note><brief>Move Quadword from XMM to MMX Technology Register</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D7">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PMOVMSKB</mnem>
<dst depend="no"><a>G</a><t>dqp</t></dst>
<src><a>N</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Move Byte Mask</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PMOVMSKB</mnem>
<dst depend="no"><a>G</a><t>dqp</t></dst>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Move Byte Mask</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D8">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBUSB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBUSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="D9">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBUSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBUSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="DA">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PMINUB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Minimum of Packed Unsigned Byte Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PMINUB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Minimum of Packed Unsigned Byte Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="DB">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PAND</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>logical</grp1>
<note><brief>Logical AND</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PAND</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>logical</grp2>
<note><brief>Logical AND</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="DC">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDUSB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDUSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="DD">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDUSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDUSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Unsigned Integers with Unsigned Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="DE">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PMAXUB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Maximum of Packed Unsigned Byte Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PMAXUB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Maximum of Packed Unsigned Byte Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="DF">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PANDN</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>logical</grp1>
<note><brief>Logical AND NOT</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PANDN</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>logical</grp2>
<note><brief>Logical AND NOT</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E0">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PAVGB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Average Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PAVGB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Average Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E1">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSRAW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRAW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E2">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSRAD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSRAD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Right Arithmetic</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E3">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PAVGW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Average Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PAVGW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Average Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E4">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PMULHUW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Multiply Packed Unsigned Integers and Store High Result</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PMULHUW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Multiply Packed Unsigned Integers and Store High Result</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E5">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PMULHW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Multiply Packed Signed Integers and Store High Result</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PMULHW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Packed Signed Integers and Store High Result</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E6">
<entry r="yes">
<pref>F2</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTPD2DQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Packed Double-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTTPD2DQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>pd</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert with Trunc. Packed Double-FP Values to <!--1.11 Packed -->DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>F3</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>CVTDQ2PD</mnem>
<dst><a>V</a><t>pd</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>pcksclr</grp1>
<grp2>conver</grp2>
<note><brief>Convert Packed DW Integers to <!--1.11 Packed -->Double-FP Values</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E7">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>MOVNTQ</mnem>
<dst depend="no"><a>M</a><t>q</t></dst>
<src><a>P</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store of Quadword Using Non-Temporal Hint</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MOVNTDQ</mnem>
<dst depend="no"><a>M</a><t>dq</t></dst>
<src><a>V</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store Double Quadword Using Non-Temporal Hint</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E8">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBSB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Signed Integers with Signed Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Signed Integers with Signed Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="E9">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Signed Integers with Signed Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Signed Integers with Signed Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EA">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PMINSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Minimum of Packed Signed Word Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PMINSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Minimum of Packed Signed Word Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EB">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>POR</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>logical</grp1>
<note><brief>Bitwise Logical OR</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>POR</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>logical</grp2>
<note><brief>Bitwise Logical OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EC">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDSB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Signed Integers with Signed Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDSB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Signed Integers with Signed Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="ED">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Signed Integers with Signed Saturation</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Signed Integers with Signed Saturation</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EE">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PMAXSW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Maximum of Packed Signed Word Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PMAXSW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Maximum of Packed Signed Word Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="EF">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PXOR</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>logical</grp1>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PXOR</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>logical</grp2>
<note><brief>Logical Exclusive OR</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F0">
<entry r="yes">
<pref>F2</pref>
<proc_start lat_step="yes">10</proc_start>
<syntax>
<mnem>LDDQU</mnem>
<dst depend="no"><a>V</a><t>dq</t></dst>
<src><a>M</a><t>dq</t></src>
</syntax>
<instr_ext>sse3</instr_ext>
<grp1>cachect</grp1>
<note><brief>Load Unaligned Integer 128 Bits</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F1">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSLLW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F2">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSLLD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F3">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSLLQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>shift</grp1>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSLLQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>shift</grp2>
<note><brief>Shift Packed Data Left Logical</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F4">
<entry r="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>PMULUDQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Packed Unsigned DW Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PMULUDQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Multiply Packed Unsigned DW Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F5">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PMADDWD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>d</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Multiply and Add Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PMADDWD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Multiply and Add Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F6">
<entry r="yes">
<proc_start>09</proc_start>
<syntax>
<mnem>PSADBW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Compute Sum of Absolute Differences</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>09</proc_start>
<syntax>
<mnem>PSADBW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>simdint</grp1>
<note><brief>Compute Sum of Absolute Differences</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F7">
<entry r="yes" doc_ref="gen_note_MASKMOVQ_0FF7">
<proc_start>09</proc_start>
<syntax>
<mnem>MASKMOVQ</mnem>
<dst type="q" address="BD" depend="no" displayed="no">(DS:)[rDI]</dst>
<dst><a>P</a><t>q</t></dst>
<src><a>N</a><t>q</t></src>
</syntax>
<instr_ext>sse1</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store Selected Bytes of Quadword</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>MASKMOVDQU</mnem>
<dst type="dq" address="BD" depend="no" displayed="no">(DS:)[rDI]</dst>
<src><a>V</a><t>dq</t></src>
<src><a>U</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>cachect</grp1>
<note><brief>Store Selected Bytes of Double Quadword</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F8">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="F9">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FA">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PSUBD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Subtract Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FB">
<entry r="yes">
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBQ</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Quadword Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PSUBQ</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Subtract Packed Quadword Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FC">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDB</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDB</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FD">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDW</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDW</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Integers</brief></note>
</entry>
</pri_opcd>
<pri_opcd value="FE">
<entry r="yes">
<proc_start>06</proc_start>
<syntax>
<mnem>PADDD</mnem>
<dst><a>P</a><t>q</t></dst>
<src><a>Q</a><t>q</t></src>
</syntax>
<instr_ext>mmx</instr_ext>
<grp1>arith</grp1>
<note><brief>Add Packed Integers</brief></note>
</entry>
<entry r="yes">
<pref>66</pref>
<proc_start>10</proc_start>
<syntax>
<mnem>PADDD</mnem>
<dst><a>V</a><t>dq</t></dst>
<src><a>W</a><t>dq</t></src>
</syntax>
<instr_ext>sse2</instr_ext>
<grp1>simdint</grp1>
<grp2>arith</grp2>
<note><brief>Add Packed Integers</brief></note>
</entry>
</pri_opcd>
<!-- 0FFF: invalid -->
</two-byte>
<!-- General and ring notes are not a part of public XML source -->
<gen_notes>
<gen_note id="gen_note_opcd_POP_CS_0F"/>
<gen_note id="gen_note_branch_prefixes"/>
<gen_note id="gen_note_plain_F390"/>
<gen_note id="gen_note_SAHF_9E_LAHF_9F"/>
<gen_note id="gen_note_SAL_C0_4_C1_4_D0_4_D1_4"/>
<gen_note id="gen_note_undefined_D6_F1"/>
<gen_note id="gen_note_u_SALC_D6"/>
<gen_note id="gen_note_FSTP1_D9_3_FSTP8_DF_2_FSTP9_DF_3"/>
<gen_note id="gen_note_FSTP1_D9_3_not_true_alias"/>
<gen_note id="gen_note_FNENI_DBE0_FNDISI_DBE1"/>
<gen_note id="gen_note_FNSETPM_DBE4"/>
<gen_note id="gen_note_FCOM2_DC_2"/>
<gen_note id="gen_note_FCOMP3_DC_3_FCOMP5_DE_2"/>
<gen_note id="gen_note_FXCH4_DD_1_FXCH7_DF_1"/>
<gen_note id="gen_note_FFREEP_DF_1"/>
<gen_note id="gen_note_x87_fpu_undoc_aliases"/>
<gen_note id="gen_note_u_INT1_ICEBP_F1"/>
<gen_note id="gen_note_REP_F2_F3"/>
<gen_note id="gen_note_TEST_F6_1_F7_1"/>
<gen_note id="gen_note_CALLF_FF_3_JMPF_FF_5"/>
<gen_note id="gen_note_SMSW_0F01_4"/>
<gen_note id="gen_note_u_LOADALL_0F05_0F07"/>
<gen_note id="gen_note_SYSCALL_0F05"/>
<gen_note id="gen_note_NOP_0F0D"/>
<gen_note id="gen_note_MOV_CR_0F20_0F22"/>
<gen_note id="gen_note_u_MOV_CR_DR_TR_0F20_0F21_0F22_0F23_0F24_0F26"/>
<gen_note id="gen_note_SYSENTER_0F34"/>
<gen_note id="gen_note_SYSEXIT_0F35"/>
<gen_note id="gen_note_GETSEC_0F37"/>
<gen_note id="gen_note_MOVQ_0F6E_660F6E_0F7E_660F7E"/>
<gen_note id="gen_note_SETcc_0F90-0F9F"/>
<gen_note id="gen_note_CMPXCHG_0FB0_0FB1"/>
<gen_note id="gen_note_LSS_0FB2_LFS_0FB4_LGS_0FB5"/>
<gen_note id="gen_note_sug_UD_0FB9"/>
<gen_note id="gen_note_BSF_0FBC_BSR_0FBD"/>
<gen_note id="gen_note_CMPXCHG8B_CMPXCHG16B_0FC7_1"/>
<gen_note id="gen_note_BSWAP_0FC8"/>
<gen_note id="gen_note_short_near_jmp"/>
<gen_note id="gen_note_VMX_vs_SVM"/>
<gen_note id="gen_note_SSE4_amd"/>
</gen_notes>
<ring_notes>
<ring_note id="rflags_iopl"/>
<ring_note id="cr4_tsd"/>
<ring_note id="cr4_pce"/>
</ring_notes>
</x86reference>
<!-- Keep this comment at the end of the file
Local variables:
mode: xml
sgml-omittag:nil
sgml-shorttag:nil
sgml-namecase-general:nil
sgml-general-insert-case:lower
sgml-minimize-attributes:nil
sgml-always-quote-attributes:t
sgml-indent-step:2
sgml-indent-data:nil
sgml-parent-document:nil
sgml-exposed-tags:nil
sgml-local-catalogs:nil
sgml-local-ecat-files:nil
End:
-->