Document VERR/VERW and helper function
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cpux86-ta.js
18
cpux86-ta.js
@ -4787,7 +4787,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, interrupt) {
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}
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//utility function for op_VERR_VERW
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function rf(selector, ud) {
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function segment_isnt_accessible(selector, is_verw) {
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var e, descriptor_low4bytes, descriptor_high4bytes, rpl, dpl, cpl_var;
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if ((selector & 0xfffc) == 0)
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return 0;
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@ -4796,13 +4796,13 @@ CPU_X86.prototype.exec_internal = function(N_cycles, interrupt) {
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return 0;
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descriptor_low4bytes = e[0];
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descriptor_high4bytes = e[1];
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if (!(descriptor_high4bytes & (1 << 12)))
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if (!(descriptor_high4bytes & (1 << 12))) // s bit (system == 0)
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return 0;
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rpl = selector & 3;
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dpl = (descriptor_high4bytes >> 13) & 3;
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cpl_var = cpu.cpl;
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if (descriptor_high4bytes & (1 << 11)) {
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if (ud) {
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if (descriptor_high4bytes & (1 << 11)) { // code == 1, data == 0
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if (is_verw) { // code segments are never writable
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return 0;
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} else {
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if (!(descriptor_high4bytes & (1 << 9)))
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@ -4813,17 +4813,19 @@ CPU_X86.prototype.exec_internal = function(N_cycles, interrupt) {
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}
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}
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} else {
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if (dpl < cpl_var || dpl < rpl)
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if (dpl < cpl_var || dpl < rpl) // data segments are always readable, if privilege is sufficient
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return 0;
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if (ud && !(descriptor_high4bytes & (1 << 9)))
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if (is_verw && !(descriptor_high4bytes & (1 << 9))) //writable data segment
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return 0;
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}
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return 1;
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}
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function op_VERR_VERW(selector, ud) {
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function op_VERR_VERW(selector, is_verw) {
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var z;
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z = rf(selector, ud);
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z = segment_isnt_accessible(selector, is_verw);
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_src = get_conditional_flags();
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// clear eflags.zf if selector is accessible and (readable (for VERR) or writable (for VERW))
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if (z)
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_src |= 0x0040;
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else
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