From ae470ba5088285b1eada72ae1f474f39964b431e Mon Sep 17 00:00:00 2001 From: Anselm Levskaya Date: Wed, 21 Dec 2011 21:04:09 -0800 Subject: [PATCH] autoannotated the opcodes --- cpux86-ta.js | 360 +- readme.md | 15 +- refactoring_hacks/autocomments.py | 99 + refactoring_hacks/onebyte_dict.json | 1 + refactoring_hacks/twobyte_dict.json | 1 + refactoring_hacks/x86opcodes.xml | 15151 +++++++++++++++++++++++++ refactoring_hacks/x86reference.xml | 15197 ++++++++++++++++++++++++++ 7 files changed, 30643 insertions(+), 181 deletions(-) create mode 100644 refactoring_hacks/autocomments.py create mode 100644 refactoring_hacks/onebyte_dict.json create mode 100644 refactoring_hacks/twobyte_dict.json create mode 100644 refactoring_hacks/x86opcodes.xml create mode 100644 refactoring_hacks/x86reference.xml diff --git a/cpux86-ta.js b/cpux86-ta.js index d7c1fe6..e23547f 100644 --- a/cpux86-ta.js +++ b/cpux86-ta.js @@ -5662,7 +5662,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { OPbyte |= (CS_flags = init_CS_flags) & 0x0100; Fd: for (; ; ) { switch (OPbyte) { - case 0x66://Operand-size override prefix + case 0x66:// Operand-size override prefix if (CS_flags == init_CS_flags) Cd(Nb, OPbyte); if (init_CS_flags & 0x0100) @@ -5672,7 +5672,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { OPbyte = phys_mem8[mem_ptr++]; OPbyte |= (CS_flags & 0x0100); break; - case 0x67://Address-size override prefix + case 0x67:// Address-size override prefix if (CS_flags == init_CS_flags) Cd(Nb, OPbyte); if (init_CS_flags & 0x0080) @@ -5703,9 +5703,9 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { OPbyte = phys_mem8[mem_ptr++]; OPbyte |= (CS_flags & 0x0100); break; - case 0x26://ES ES segment override prefix + case 0x26://ES ES ES segment override prefix case 0x2e://CS CS segment override prefix - case 0x36://SS SS segment override prefix + case 0x36://SS SS SS segment override prefix case 0x3e://DS DS segment override prefix if (CS_flags == init_CS_flags) Cd(Nb, OPbyte); @@ -5713,8 +5713,8 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { OPbyte = phys_mem8[mem_ptr++]; OPbyte |= (CS_flags & 0x0100); break; - case 0x64://FS FS segment override prefix - case 0x65://GS GS segment override prefix + case 0x64://FS FS FS segment override prefix + case 0x65://GS GS GS segment override prefix if (CS_flags == init_CS_flags) Cd(Nb, OPbyte); CS_flags = (CS_flags & ~0x000f) | ((OPbyte & 7) + 1); @@ -5748,7 +5748,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } regs[OPbyte & 7] = x; break Fd; - case 0x88://MOV r/m8 r8 + case 0x88://MOV Gb Eb Move mem8 = phys_mem8[mem_ptr++]; register_1 = (mem8 >> 3) & 7; x = (regs[register_1 & 3] >> ((register_1 & 4) << 1)); @@ -5768,7 +5768,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } } break Fd; - case 0x89://MOV r/m16/32 r16/32 + case 0x89://MOV Gvqp Evqp Move mem8 = phys_mem8[mem_ptr++]; x = regs[(mem8 >> 3) & 7]; if ((mem8 >> 6) == 3) { @@ -5879,7 +5879,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { regs[0] = regs[register_1]; regs[register_1] = x; break Fd; - case 0x86://XCHG r8 r/m8 Exchange Register/Memory with Register + case 0x86://XCHG Gb Exchange Register/Memory with Register mem8 = phys_mem8[mem_ptr++]; register_1 = (mem8 >> 3) & 7; if ((mem8 >> 6) == 3) { @@ -5893,7 +5893,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } set_either_two_bytes_of_reg_ABCD(register_1, x); break Fd; - case 0x87://XCHG r16/32 r/m16/32 Exchange Register/Memory with Register + case 0x87://XCHG Gvqp Exchange Register/Memory with Register mem8 = phys_mem8[mem_ptr++]; register_1 = (mem8 >> 3) & 7; if ((mem8 >> 6) == 3) { @@ -5943,14 +5943,14 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { case 0xc5://LDS DS r16/32 m16:16/32 Load Far Pointer Uf(3); break Fd; - case 0x00://ADD r/m8 r8 Add - case 0x08://OR r/m8 r8 Logical Inclusive OR - case 0x10://ADC r/m8 r8 Add with Carry - case 0x18://SBB r/m8 r8 Integer Subtraction with Borrow - case 0x20://AND r/m8 r8 Logical AND - case 0x28://SUB r/m8 r8 Subtract - case 0x30://XOR r/m8 r8 Logical Exclusive OR - case 0x38://CMP r/m8 r8 Compare Two Operands + case 0x00://ADD Gb Eb Add + case 0x08://OR Gb Eb Logical Inclusive OR + case 0x10://ADC Gb Eb Add with Carry + case 0x18://SBB Gb Eb Integer Subtraction with Borrow + case 0x20://AND Gb Eb Logical AND + case 0x28://SUB Gb Eb Subtract + case 0x30://XOR Gb Eb Logical Exclusive OR + case 0x38://CMP Eb Compare Two Operands mem8 = phys_mem8[mem_ptr++]; conditional_var = OPbyte >> 3; register_1 = (mem8 >> 3) & 7; @@ -5970,7 +5970,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } } break Fd; - case 0x01://ADD r/m16/32 r16/32 Add + case 0x01://ADD Gvqp Evqp Add mem8 = phys_mem8[mem_ptr++]; y = regs[(mem8 >> 3) & 7]; if ((mem8 >> 6) == 3) { @@ -5991,12 +5991,12 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { st32_mem8_write(x); } break Fd; - case 0x09://OR r/m16/32 r16/32 Logical Inclusive OR - case 0x11://ADC r/m16/32 r16/32 Add with Carry - case 0x19://SBB r/m16/32 r16/32 Integer Subtraction with Borrow - case 0x21://AND r/m16/32 r16/32 Logical AND - case 0x29://SUB r/m16/32 r16/32 Subtract - case 0x31://XOR r/m16/32 r16/32 Logical Exclusive OR + case 0x09://OR Gvqp Evqp Logical Inclusive OR + case 0x11://ADC Gvqp Evqp Add with Carry + case 0x19://SBB Gvqp Evqp Integer Subtraction with Borrow + case 0x21://AND Gvqp Evqp Logical AND + case 0x29://SUB Gvqp Evqp Subtract + case 0x31://XOR Gvqp Evqp Logical Exclusive OR mem8 = phys_mem8[mem_ptr++]; conditional_var = OPbyte >> 3; y = regs[(mem8 >> 3) & 7]; @@ -6010,7 +6010,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { st32_mem8_write(x); } break Fd; - case 0x39://CMP r/m16/32 r16/32 Compare Two Operands + case 0x39://CMP Evqp Compare Two Operands mem8 = phys_mem8[mem_ptr++]; conditional_var = OPbyte >> 3; y = regs[(mem8 >> 3) & 7]; @@ -6031,13 +6031,13 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } } break Fd; - case 0x02://ADD r8 r/m8 Add + case 0x02://ADD Eb Gb Add case 0x0a://OR r8 r/m8 Logical Inclusive OR - case 0x12://ADC r8 r/m8 Add with Carry + case 0x12://ADC Eb Gb Add with Carry case 0x1a://SBB r8 r/m8 Integer Subtraction with Borrow - case 0x22://AND r8 r/m8 Logical AND + case 0x22://AND Eb Gb Logical AND case 0x2a://SUB r8 r/m8 Subtract - case 0x32://XOR r8 r/m8 Logical Exclusive OR + case 0x32://XOR Eb Gb Logical Exclusive OR case 0x3a://CMP r8 r/m8 Compare Two Operands mem8 = phys_mem8[mem_ptr++]; conditional_var = OPbyte >> 3; @@ -6051,7 +6051,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } set_either_two_bytes_of_reg_ABCD(register_1, do_8bit_math(conditional_var, (regs[register_1 & 3] >> ((register_1 & 4) << 1)), y)); break Fd; - case 0x03: + case 0x03://ADD Evqp Gvqp Add mem8 = phys_mem8[mem_ptr++]; register_1 = (mem8 >> 3) & 7; if ((mem8 >> 6) == 3) { @@ -6067,11 +6067,11 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; case 0x0b: - case 0x13: + case 0x13://ADC Evqp Gvqp Add with Carry case 0x1b: - case 0x23: + case 0x23://AND Evqp Gvqp Logical AND case 0x2b: - case 0x33: + case 0x33://XOR Evqp Gvqp Logical Exclusive OR mem8 = phys_mem8[mem_ptr++]; conditional_var = OPbyte >> 3; register_1 = (mem8 >> 3) & 7; @@ -6099,19 +6099,19 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { _op = 8; } break Fd; - case 0x04: + case 0x04://ADD Ib AL Add case 0x0c: - case 0x14: + case 0x14://ADC Ib AL Add with Carry case 0x1c: - case 0x24: + case 0x24://AND Ib AL Logical AND case 0x2c: - case 0x34: + case 0x34://XOR Ib AL Logical Exclusive OR case 0x3c: y = phys_mem8[mem_ptr++]; conditional_var = OPbyte >> 3; set_either_two_bytes_of_reg_ABCD(0, do_8bit_math(conditional_var, regs[0] & 0xff, y)); break Fd; - case 0x05: + case 0x05://ADD Ivds rAX Add { y = phys_mem8[mem_ptr] | (phys_mem8[mem_ptr + 1] << 8) | (phys_mem8[mem_ptr + 2] << 16) | (phys_mem8[mem_ptr + 3] << 24); mem_ptr += 4; @@ -6123,9 +6123,9 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; case 0x0d: - case 0x15: + case 0x15://ADC Ivds rAX Add with Carry case 0x1d: - case 0x25: + case 0x25://AND Ivds rAX Logical AND case 0x2d: { y = phys_mem8[mem_ptr] | (phys_mem8[mem_ptr + 1] << 8) | (phys_mem8[mem_ptr + 2] << 16) | (phys_mem8[mem_ptr + 3] << 24); @@ -6134,7 +6134,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { conditional_var = OPbyte >> 3; regs[0] = do_32bit_math(conditional_var, regs[0], y); break Fd; - case 0x35: + case 0x35://XOR Ivds rAX Logical Exclusive OR { y = phys_mem8[mem_ptr] | (phys_mem8[mem_ptr + 1] << 8) | (phys_mem8[mem_ptr + 2] << 16) | (phys_mem8[mem_ptr + 3] << 24); mem_ptr += 4; @@ -6155,8 +6155,8 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { _op = 8; } break Fd; - case 0x80: - case 0x82: + case 0x80://ADD Ib Eb Add + case 0x82://ADD Ib Eb Add mem8 = phys_mem8[mem_ptr++]; conditional_var = (mem8 >> 3) & 7; if ((mem8 >> 6) == 3) { @@ -6176,7 +6176,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } } break Fd; - case 0x81: + case 0x81://ADD Ivds Evqp Add mem8 = phys_mem8[mem_ptr++]; conditional_var = (mem8 >> 3) & 7; if (conditional_var == 7) { @@ -6215,7 +6215,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } } break Fd; - case 0x83: + case 0x83://ADD Ibs Evqp Add mem8 = phys_mem8[mem_ptr++]; conditional_var = (mem8 >> 3) & 7; if (conditional_var == 7) { @@ -6245,14 +6245,14 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } } break Fd; - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x44: - case 0x45: - case 0x46: - case 0x47: + case 0x40://INC Zv Increment by 1 + case 0x41://REX.B Extension of r/m field, base field, or opcode reg field + case 0x42://REX.X Extension of SIB index field + case 0x43://REX.XB REX.X and REX.B combination + case 0x44://REX.R Extension of ModR/M reg field + case 0x45://REX.RB REX.R and REX.B combination + case 0x46://REX.RX REX.R and REX.X combination + case 0x47://REX.RXB REX.R, REX.X and REX.B combination register_1 = OPbyte & 7; { if (_op < 25) { @@ -6263,8 +6263,8 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { _op = 27; } break Fd; - case 0x48: - case 0x49: + case 0x48://DEC Zv Decrement by 1 + case 0x49://REX.WB REX.W and REX.B combination case 0x4a: case 0x4b: case 0x4c: @@ -6293,7 +6293,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { z = ((phys_mem8[mem_ptr++] << 24) >> 24); regs[register_1] = Wc(y, z); break Fd; - case 0x69: + case 0x69://IMUL Evqp Gvqp Signed Multiply mem8 = phys_mem8[mem_ptr++]; register_1 = (mem8 >> 3) & 7; if ((mem8 >> 6) == 3) { @@ -6308,7 +6308,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } regs[register_1] = Wc(y, z); break Fd; - case 0x84: + case 0x84://TEST Eb Logical Compare mem8 = phys_mem8[mem_ptr++]; if ((mem8 >> 6) == 3) { register_0 = mem8 & 7; @@ -6324,7 +6324,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { _op = 12; } break Fd; - case 0x85: + case 0x85://TEST Evqp Logical Compare mem8 = phys_mem8[mem_ptr++]; if ((mem8 >> 6) == 3) { x = regs[mem8 & 7]; @@ -6683,15 +6683,15 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; //98 CBW AX AL Convert Byte to Word - case 0x98: + case 0x98://CBW AL AX Convert Byte to Word regs[0] = (regs[0] << 16) >> 16; break Fd; //99 CWD DX AX Convert Word to Doubleword - case 0x99: + case 0x99://CWD AX DX Convert Word to Doubleword regs[2] = regs[0] >> 31; break Fd; //50+r PUSH r16/32 Push Word, Doubleword or Quadword Onto the Stack - case 0x50: + case 0x50://PUSH Zv SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack case 0x51: case 0x52: case 0x53: @@ -6716,7 +6716,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; //58+r POP r16/32 Pop a Value from the Stack - case 0x58: + case 0x58://POP SS:[rSP] Zv Pop a Value from the Stack case 0x59: case 0x5a: case 0x5b: @@ -6735,11 +6735,11 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { regs[OPbyte & 7] = x; break Fd; //60 01+ PUSHA AX CX DX ... Push All General-Purpose Registers - case 0x60: + case 0x60://PUSHA AX SS:[rSP] Push All General-Purpose Registers Kf(); break Fd; //61 01+ POPA DI SI BP ... Pop All General-Purpose Registers - case 0x61: + case 0x61://POPA SS:[rSP] DI Pop All General-Purpose Registers Mf(); break Fd; //8F 0 POP r/m16/32 Pop a Value from the Stack @@ -6761,7 +6761,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; //68 01+ PUSH imm16/32 Push Word, Doubleword or Quadword Onto the Stack - case 0x68: + case 0x68://PUSH Ivs SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack { x = phys_mem8[mem_ptr] | (phys_mem8[mem_ptr + 1] << 8) | (phys_mem8[mem_ptr + 2] << 16) | (phys_mem8[mem_ptr + 3] << 24); mem_ptr += 4; @@ -6845,14 +6845,14 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { break Bg; } break Fd; - case 0x06: + case 0x06://PUSH ES SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack case 0x0e: - case 0x16: + case 0x16://PUSH SS SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack case 0x1e: xd(cpu.segs[OPbyte >> 3].selector); break Fd; - case 0x07: - case 0x17: + case 0x07://POP SS:[rSP] ES Pop a Value from the Stack + case 0x17://POP SS:[rSP] SS Pop a Value from the Stack case 0x1f: Ie(OPbyte >> 3, Ad() & 0xffff); Bd(); @@ -7029,7 +7029,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { y = Ob(); Oe(y, x); break Fd; - case 0x70: + case 0x70://JO Jbs Jump short if overflow (OF=1) if (check_overflow()) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7037,7 +7037,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x71: + case 0x71://JNO Jbs Jump short if not overflow (OF=0) if (!check_overflow()) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7045,7 +7045,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x72: + case 0x72://JB Jbs Jump short if below/not above or equal/carry (CF=1) if (check_carry()) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7053,7 +7053,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x73: + case 0x73://JNB Jbs Jump short if not below/above or equal/not carry (CF=0) if (!check_carry()) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7061,7 +7061,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x74: + case 0x74://JZ Jbs Jump short if zero/equal (ZF=0) if ((_dst == 0)) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7069,7 +7069,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x75: + case 0x75://JNZ Jbs Jump short if not zero/not equal (ZF=1) if (!(_dst == 0)) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7077,7 +7077,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x76: + case 0x76://JBE Jbs Jump short if below or equal/not above (CF=1 AND ZF=1) if (ad()) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7085,7 +7085,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x77: + case 0x77://JNBE Jbs Jump short if not below or equal/above (CF=0 AND ZF=0) if (!ad()) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7093,7 +7093,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x78: + case 0x78://JS Jbs Jump short if sign (SF=1) if ((_op == 24 ? ((_src >> 7) & 1) : (_dst < 0))) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7101,7 +7101,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { mem_ptr = (mem_ptr + 1) >> 0; } break Fd; - case 0x79: + case 0x79://JNS Jbs Jump short if not sign (SF=0) if (!(_op == 24 ? ((_src >> 7) & 1) : (_dst < 0))) { x = ((phys_mem8[mem_ptr++] << 24) >> 24); mem_ptr = (mem_ptr + x) >> 0; @@ -7267,7 +7267,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { break Bg; } break Fd; - case 0x90: + case 0x90://XCHG Zvqp Exchange Register/Memory with Register break Fd; case 0xcc: y = (eip + mem_ptr - initial_mem_ptr); @@ -7287,7 +7287,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; //62 r 01+ f BOUND r16/32 m16/32&16/32 eFlags ..i..... ..i..... ..i..... Check Array Index Against Bounds - case 0x62: + case 0x62://BOUND Gv SS:[rSP] Check Array Index Against Bounds Hf(); break Fd; // F5 CMC .......c .......c .......c Complement Carry Flag @@ -7518,13 +7518,13 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { break Bg; } break Fd; - case 0x27: + case 0x27://DAA AL Decimal Adjust AL after Addition Df(); break Fd; case 0x2f: Ff(); break Fd; - case 0x37: + case 0x37://AAA AL ASCII Adjust After Addition zf(); break Fd; case 0x3f: @@ -7538,7 +7538,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { x = phys_mem8[mem_ptr++]; yf(x); break Fd; - case 0x63: + case 0x63://ARPL Ew Adjust RPL Field of Segment Selector tf(); break Fd; case 0xd6: @@ -7584,16 +7584,16 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { JNG rel16/32 0F 8F 03+ JNLE rel16/32 o..sz... Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF)) */ - case 0x80: - case 0x81: - case 0x82: - case 0x83: - case 0x84: - case 0x85: - case 0x86: - case 0x87: - case 0x88: - case 0x89: + case 0x80://JO Jvds Jump short if overflow (OF=1) + case 0x81://JNO Jvds Jump short if not overflow (OF=0) + case 0x82://JB Jvds Jump short if below/not above or equal/carry (CF=1) + case 0x83://JNB Jvds Jump short if not below/above or equal/not carry (CF=0) + case 0x84://JZ Jvds Jump short if zero/equal (ZF=0) + case 0x85://JNZ Jvds Jump short if not zero/not equal (ZF=1) + case 0x86://JBE Jvds Jump short if below or equal/not above (CF=1 AND ZF=1) + case 0x87://JNBE Jvds Jump short if not below or equal/above (CF=0 AND ZF=0) + case 0x88://JS Jvds Jump short if sign (SF=1) + case 0x89://JNS Jvds Jump short if not sign (SF=0) case 0x8a: case 0x8b: case 0x8c: @@ -7607,16 +7607,16 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { if (check_status_bits_for_jump(OPbyte & 0xf)) mem_ptr = (mem_ptr + x) >> 0; break Fd; - case 0x90: - case 0x91: - case 0x92: - case 0x93: - case 0x94: - case 0x95: - case 0x96: - case 0x97: - case 0x98: - case 0x99: + case 0x90://SETO Eb Set Byte on Condition - overflow (OF=1) + case 0x91://SETNO Eb Set Byte on Condition - not overflow (OF=0) + case 0x92://SETB Eb Set Byte on Condition - below/not above or equal/carry (CF=1) + case 0x93://SETNB Eb Set Byte on Condition - not below/above or equal/not carry (CF=0) + case 0x94://SETZ Eb Set Byte on Condition - zero/equal (ZF=0) + case 0x95://SETNZ Eb Set Byte on Condition - not zero/not equal (ZF=1) + case 0x96://SETBE Eb Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1) + case 0x97://SETNBE Eb Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0) + case 0x98://SETS Eb Set Byte on Condition - sign (SF=1) + case 0x99://SETNS Eb Set Byte on Condition - not sign (SF=0) case 0x9a: case 0x9b: case 0x9c: @@ -7632,16 +7632,16 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { st8_mem8_write(x); } break Fd; - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x44: - case 0x45: - case 0x46: - case 0x47: - case 0x48: - case 0x49: + case 0x40://CMOVO Evqp Gvqp Conditional Move - overflow (OF=1) + case 0x41://CMOVNO Evqp Gvqp Conditional Move - not overflow (OF=0) + case 0x42://CMOVB Evqp Gvqp Conditional Move - below/not above or equal/carry (CF=1) + case 0x43://CMOVNB Evqp Gvqp Conditional Move - not below/above or equal/not carry (CF=0) + case 0x44://CMOVZ Evqp Gvqp Conditional Move - zero/equal (ZF=0) + case 0x45://CMOVNZ Evqp Gvqp Conditional Move - not zero/not equal (ZF=1) + case 0x46://CMOVBE Evqp Gvqp Conditional Move - below or equal/not above (CF=1 AND ZF=1) + case 0x47://CMOVNBE Evqp Gvqp Conditional Move - not below or equal/above (CF=0 AND ZF=0) + case 0x48://CMOVS Evqp Gvqp Conditional Move - sign (SF=1) + case 0x49://CMOVNS Evqp Gvqp Conditional Move - not sign (SF=0) case 0x4a: case 0x4b: case 0x4c: @@ -7704,7 +7704,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } regs[register_1] = (((x) << 16) >> 16); break Fd; - case 0x00: + case 0x00://SLDT LDTR Mw Store Local Descriptor Table Register if (!(cpu.cr0 & (1 << 0)) || (cpu.eflags & 0x00020000)) blow_up_errcode0(6); mem8 = phys_mem8[mem_ptr++]; @@ -7752,7 +7752,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { blow_up_errcode0(6); } break Fd; - case 0x01: + case 0x01://SGDT GDTR Ms Store Global Descriptor Table Register mem8 = phys_mem8[mem_ptr++]; conditional_var = (mem8 >> 3) & 7; switch (conditional_var) { @@ -7786,11 +7786,11 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { blow_up_errcode0(6); } break Fd; - case 0x02: - case 0x03: + case 0x02://LAR Mw Gvqp Load Access Rights Byte + case 0x03://LSL Mw Gvqp Load Segment Limit qf((((CS_flags >> 8) & 1) ^ 1), OPbyte & 1); break Fd; - case 0x20: + case 0x20://MOV Cd Rd Move to/from Control Registers if (cpu.cpl != 0) blow_up_errcode0(13); mem8 = phys_mem8[mem_ptr++]; @@ -7816,7 +7816,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { regs[mem8 & 7] = x; break Fd; // 0F 22 r 03+ 0 MOV CRn r32 o..szapc o..szapc Move to/from Control Registers - case 0x22: + case 0x22://MOV Rd Cd Move to/from Control Registers if (cpu.cpl != 0) blow_up_errcode0(13); mem8 = phys_mem8[mem_ptr++]; @@ -7842,12 +7842,12 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } break Fd; // 0F 06 02+ 0 CLTS CR0 Clear Task-Switched Flag in CR0 - case 0x06: + case 0x06://CLTS CR0 Clear Task-Switched Flag in CR0 if (cpu.cpl != 0) blow_up_errcode0(13); set_CR0(cpu.cr0 & ~(1 << 3)); //Clear Task-Switched Flag in CR0 break Fd; - case 0x23: + case 0x23://MOV Rd Dd Move to/from Debug Registers if (cpu.cpl != 0) blow_up_errcode0(13); mem8 = phys_mem8[mem_ptr++]; @@ -8013,7 +8013,7 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { } regs[register_1] = Wc(regs[register_1], y); break Fd; - case 0x31: + case 0x31://RDTSC IA32_TIME_STAMP_COUNTER EAX Read Time-Stamp Counter if ((cpu.cr4 & (1 << 2)) && cpu.cpl != 0) blow_up_errcode0(13); x = current_cycle_count(); @@ -8123,53 +8123,53 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { regs[register_1] = x; break Fd; case 0x04: - case 0x05: - case 0x07: - case 0x08: - case 0x09: + case 0x05://LOADALL AX Load All of the CPU Registers + case 0x07://LOADALL EAX Load All of the CPU Registers + case 0x08://INVD Invalidate Internal Caches + case 0x09://WBINVD Write Back and Invalidate Cache case 0x0a: case 0x0b: case 0x0c: case 0x0d: case 0x0e: case 0x0f: - case 0x10: - case 0x11: - case 0x12: - case 0x13: - case 0x14: - case 0x15: - case 0x16: - case 0x17: - case 0x18: - case 0x19: + case 0x10://MOVUPS Wps Vps Move Unaligned Packed Single-FP Values + case 0x11://MOVUPS Vps Wps Move Unaligned Packed Single-FP Values + case 0x12://MOVHLPS Uq Vq Move Packed Single-FP Values High to Low + case 0x13://MOVLPS Vq Mq Move Low Packed Single-FP Values + case 0x14://UNPCKLPS Wq Vps Unpack and Interleave Low Packed Single-FP Values + case 0x15://UNPCKHPS Wq Vps Unpack and Interleave High Packed Single-FP Values + case 0x16://MOVLHPS Uq Vq Move Packed Single-FP Values Low to High + case 0x17://MOVHPS Vq Mq Move High Packed Single-FP Values + case 0x18://HINT_NOP Ev Hintable NOP + case 0x19://HINT_NOP Ev Hintable NOP case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f: - case 0x21: - case 0x24: + case 0x21://MOV Dd Rd Move to/from Debug Registers + case 0x24://MOV Td Rd Move to/from Test Registers case 0x25: - case 0x26: + case 0x26://MOV Rd Td Move to/from Test Registers case 0x27: - case 0x28: - case 0x29: + case 0x28://MOVAPS Wps Vps Move Aligned Packed Single-FP Values + case 0x29://MOVAPS Vps Wps Move Aligned Packed Single-FP Values case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f: - case 0x30: - case 0x32: - case 0x33: - case 0x34: - case 0x35: + case 0x30://WRMSR rCX MSR Write to Model Specific Register + case 0x32://RDMSR rCX rAX Read from Model Specific Register + case 0x33://RDPMC PMC EAX Read Performance-Monitoring Counters + case 0x34://SYSENTER IA32_SYSENTER_CS SS Fast System Call + case 0x35://SYSEXIT IA32_SYSENTER_CS SS Fast Return from Fast System Call case 0x36: - case 0x37: - case 0x38: + case 0x37://GETSEC EAX GETSEC Leaf Functions + case 0x38://PSHUFB Qq Pq Packed Shuffle Bytes case 0x39: case 0x3a: case 0x3b: @@ -8177,48 +8177,48 @@ CPU_X86.prototype.exec_internal = function(N_cycles, va) { case 0x3d: case 0x3e: case 0x3f: - case 0x50: - case 0x51: - case 0x52: - case 0x53: - case 0x54: - case 0x55: - case 0x56: - case 0x57: - case 0x58: - case 0x59: + case 0x50://MOVMSKPS Ups Gdqp Extract Packed Single-FP Sign Mask + case 0x51://SQRTPS Wps Vps Compute Square Roots of Packed Single-FP Values + case 0x52://RSQRTPS Wps Vps Compute Recipr. of Square Roots of Packed Single-FP Values + case 0x53://RCPPS Wps Vps Compute Reciprocals of Packed Single-FP Values + case 0x54://ANDPS Wps Vps Bitwise Logical AND of Packed Single-FP Values + case 0x55://ANDNPS Wps Vps Bitwise Logical AND NOT of Packed Single-FP Values + case 0x56://ORPS Wps Vps Bitwise Logical OR of Single-FP Values + case 0x57://XORPS Wps Vps Bitwise Logical XOR for Single-FP Values + case 0x58://ADDPS Wps Vps Add Packed Single-FP Values + case 0x59://MULPS Wps Vps Multiply Packed Single-FP Values case 0x5a: case 0x5b: case 0x5c: case 0x5d: case 0x5e: case 0x5f: - case 0x60: - case 0x61: - case 0x62: - case 0x63: - case 0x64: - case 0x65: - case 0x66: - case 0x67: - case 0x68: - case 0x69: + case 0x60://PUNPCKLBW Qd Pq Unpack Low Data + case 0x61://PUNPCKLWD Qd Pq Unpack Low Data + case 0x62://PUNPCKLDQ Qd Pq Unpack Low Data + case 0x63://PACKSSWB Qd Pq Pack with Signed Saturation + case 0x64://PCMPGTB Qd Pq Compare Packed Signed Integers for Greater Than + case 0x65://PCMPGTW Qd Pq Compare Packed Signed Integers for Greater Than + case 0x66://PCMPGTD Qd Pq Compare Packed Signed Integers for Greater Than + case 0x67://PACKUSWB Qq Pq Pack with Unsigned Saturation + case 0x68://PUNPCKHBW Qq Pq Unpack High Data + case 0x69://PUNPCKHWD Qq Pq Unpack High Data case 0x6a: case 0x6b: case 0x6c: case 0x6d: case 0x6e: case 0x6f: - case 0x70: - case 0x71: - case 0x72: - case 0x73: - case 0x74: - case 0x75: - case 0x76: - case 0x77: - case 0x78: - case 0x79: + case 0x70://PSHUFW Qq Pq Shuffle Packed Words + case 0x71://PSRLW Ib Nq Shift Packed Data Right Logical + case 0x72://PSRLD Ib Nq Shift Double Quadword Right Logical + case 0x73://PSRLQ Ib Nq Shift Packed Data Right Logical + case 0x74://PCMPEQB Qq Pq Compare Packed Data for Equal + case 0x75://PCMPEQW Qq Pq Compare Packed Data for Equal + case 0x76://PCMPEQD Qq Pq Compare Packed Data for Equal + case 0x77://EMMS Empty MMX Technology State + case 0x78://VMREAD Gd Ed Read Field from Virtual-Machine Control Structure + case 0x79://VMWRITE Gd Write Field to Virtual-Machine Control Structure case 0x7a: case 0x7b: case 0x7c: diff --git a/readme.md b/readme.md index c75d4a6..3a9174b 100644 --- a/readme.md +++ b/readme.md @@ -10,12 +10,25 @@ In the tiny off-chance someone else might be interested I'm posting this "cheat ### Status It's still absolutely ungainly, but not nearly so ungainly as the original. About a third to a half of the variables/function names have been redescribed. The names are basically long comments and will ultimately need to be redone once the whole is understood. +The core opcode execution loop has been autocommented to indicate what instruction operation the opcode refers to. + I highly recommend, by the way, the excellent [JSShaper][2] library for transforming large javascript code bases. The hacks I made from it are in this repo: a little symbol-name-transformer node.js script and an emacs function for doing this in live buffers. ### Caveat Coder This is a pedagogical reinterpretation of the original JSLinux code Copyright (c) 2011 Fabrice Bellard. -There's no alteration in the acutal algorithmic content. I do check that that it still runs, but I can't guarantee anything else. +There's no alteration in the algorithmic content. I do check that that it still runs, but I won't guarantee anything else. + +### References +Some other helpful references for understanding what's going on: + +http://ref.x86asm.net/coder32.html#xC4 +http://en.wikibooks.org/wiki/X86_Assembly/X86_Architecture +http://en.wikipedia.org/wiki/X86 +http://en.wikipedia.org/wiki/Control_register +http://en.wikipedia.org/wiki/X86_assembly_language +http://en.wikipedia.org/wiki/Translation_lookaside_buffer +http://en.wikibooks.org/wiki/Serial_Programming/8250_UART_Programming [1]: http://bellard.org/jslinux/tech.html [2]: http://sshaper.org diff --git a/refactoring_hacks/autocomments.py b/refactoring_hacks/autocomments.py new file mode 100644 index 0000000..1c274ab --- /dev/null +++ b/refactoring_hacks/autocomments.py @@ -0,0 +1,99 @@ +# quick hack: +# grabs data from XML file describing opcodes from http://ref.x86asm.net +# then autocomments the cpux86 emulator code +# +# (super brittle hack) +# + +from BeautifulSoup import BeautifulStoneSoup #thank you soup, fuck XML parsers +import json, re + +# +# Let me reiterate how much I despise scraping data from XML +# +infile = open("x86opcodes.xml","r").read() +soup=BeautifulStoneSoup(infile) +onesies=soup.find('one-byte').findAll('pri_opcd') +twosies=soup.find('two-byte').findAll('pri_opcd') + +def hexRepOfOp(op): + i=int(op['value'],16) + if i < 16: + return "0x0"+hex(i)[2:] + else: + return "0x" +hex(i)[2:] +def mnem(op): + res = op.find('mnem') + if res: + return res.string + else: + return "" +def src(op): + res = op.find('syntax').find('src') + if res: + return res.getText() + else: + return "" +def dst(op): + res = op.find('syntax').find('dst') + if res: + return res.getText() + else: + return "" +def note(op): + res = op.find('note').find('brief') + if res: + return res.getText() + else: + return "" +def opstr(op): + return mnem(op)+" "+src(op)+" "+dst(op)+" "+note(op) + +onedict = {} +for op in onesies: + onedict[hexRepOfOp(op)] = opstr(op) +twodict = {} +for op in twosies: + twodict[hexRepOfOp(op)] = opstr(op) + +# barf some temporaries just for reference later +outfile=open("onebyte_dict.json",'w') +json.dump(onedict,outfile) +outfile.close() + +outfile=open("twobyte_dict.json",'w') +json.dump(twodict,outfile) +outfile.close() + +# now transform source file +caseline = re.compile("(\s+case )(0x[0-9]+):.*") + +emulatorlines = open("cpux86-ta.js","r").readlines() +newlines=[] +for i,line in enumerate(emulatorlines): + if i< 5662: + newlines.append(line) + if 5662<=i<7551: #one-byte instructions + linematch=caseline.match(line) + if linematch: + try: + newlines.append(linematch.group(1)+linematch.group(2)+"://"+onedict[linematch.group(2)]+"\n") + except KeyError: + newlines.append(line) + else: + newlines.append(line) + if 7551<=i<8291: #two-byte instructions + linematch=caseline.match(line) + if linematch: + try: + newlines.append(linematch.group(1)+linematch.group(2)+"://"+twodict[linematch.group(2)]+"\n") + except KeyError: + newlines.append(line) + else: + newlines.append(line) + if 8291<=i: + newlines.append(line) + +outfile=open("cpux86-ta-auto-annotated.js",'w') +outfile.writelines(newlines) +outfile.close() diff --git a/refactoring_hacks/onebyte_dict.json b/refactoring_hacks/onebyte_dict.json new file mode 100644 index 0000000..e68cb10 --- /dev/null +++ b/refactoring_hacks/onebyte_dict.json @@ -0,0 +1 @@ +{"0x3e": "DS DS DS segment override prefix", "0x3d": "CMP rAX Compare Two Operands", "0xe4": "IN Ib AL Input from Port", "0x3f": "AAS AL ASCII Adjust AL After Subtraction", "0x3a": "CMP Gb Compare Two Operands", "0x3c": "CMP AL Compare Two Operands", "0x3b": "CMP Gvqp Compare Two Operands", "0xfa": "CLI Clear Interrupt Flag", "0xda": "FIADD Mdi ST Add", "0xec": "IN DX AL Input from Port", "0x28": "SUB Gb Eb Subtract", "0x29": "SUB Gvqp Evqp Subtract", "0xf8": "CLC Clear Carry Flag", "0xeb": "JMP Jbs Jump", "0x22": "AND Eb Gb Logical AND", "0x23": "AND Evqp Gvqp Logical AND", "0x20": "AND Gb Eb Logical AND", "0x21": "AND Gvqp Evqp Logical AND", "0x26": "ES ES ES segment override prefix", "0x27": "DAA AL Decimal Adjust AL after Addition", "0x24": "AND Ib AL Logical AND", "0x25": "AND Ivds rAX Logical AND", "0xef": "OUT eAX DX Output to Port", "0xe2": "LOOP Jbs eCX Decrement count; Jump short if count!=0", "0xee": "OUT AL DX Output to Port", "0xed": "IN DX eAX Input from Port", "0x35": "XOR Ivds rAX Logical Exclusive OR", "0x34": "XOR Ib AL Logical Exclusive OR", "0x37": "AAA AL ASCII Adjust After Addition", "0x36": "SS SS SS segment override prefix", "0x31": "XOR Gvqp Evqp Logical Exclusive OR", "0x30": "XOR Gb Eb Logical Exclusive OR", "0x33": "XOR Evqp Gvqp Logical Exclusive OR", "0x32": "XOR Eb Gb Logical Exclusive OR", "0xd4": "AAM AL ASCII Adjust AX After Multiply", "0x39": "CMP Evqp Compare Two Operands", "0x38": "CMP Eb Compare Two Operands", "0xc0": "ROL Ib Eb Rotate", "0xe1": "LOOPZ Jbs eCX Decrement count; Jump short if count!=0 and ZF=1", "0xfe": "INC Eb Increment by 1", "0x88": "MOV Gb Eb Move", "0x89": "MOV Gvqp Evqp Move", "0x2b": "SUB Evqp Gvqp Subtract", "0x2c": "SUB Ib AL Subtract", "0xfd": "STD Set Direction Flag", "0x2a": "SUB Eb Gb Subtract", "0x2f": "DAS AL Decimal Adjust AL after Subtraction", "0xfc": "CLD Clear Direction Flag", "0x2d": "SUB Ivds rAX Subtract", "0x2e": "CS CS CS segment override prefix", "0x40": "INC Zv Increment by 1", "0x41": "REX.B Extension of r/m field, base field, or opcode reg field", "0x42": "REX.X Extension of SIB index field", "0x43": "REX.XB REX.X and REX.B combination", "0x44": "REX.R Extension of ModR/M reg field", "0x45": "REX.RB REX.R and REX.B combination", "0x46": "REX.RX REX.R and REX.X combination", "0x47": "REX.RXB REX.R, REX.X and REX.B combination", "0x48": "DEC Zv Decrement by 1", "0x49": "REX.WB REX.W and REX.B combination", "0xaf": "SCAS ES:[DI] Scan String", "0xae": "SCAS (ES:)[rDI] Scan String", "0xad": "LODS DS:[SI] AX Load String", "0xac": "LODS (DS:)[rSI] AL Load String", "0xab": "STOS AX ES:[DI] Store String", "0xaa": "STOS AL (ES:)[rDI] Store String", "0xe6": "OUT AL Ib Output to Port", "0xea": "JMPF Ap Jump", "0x4a": "REX.WX REX.W and REX.X combination", "0x4b": "REX.WXB REX.W, REX.X and REX.B combination", "0x4c": "REX.WR REX.W and REX.R combination", "0x4d": "REX.WRB REX.W, REX.R and REX.B combination", "0x4e": "REX.WRX REX.W, REX.R and REX.X combination", "0x4f": "REX.WRXB REX.W, REX.R, REX.X and REX.B combination", "0xff": "INC Evqp Increment by 1", "0x50": "PUSH Zv SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0xe5": "IN Ib eAX Input from Port", "0x58": "POP SS:[rSP] Zv Pop a Value from the Stack", "0xf4": "HLT Halt", "0xfb": "STI Set Interrupt Flag", "0xf9": "STC Set Carry Flag", "0xf6": "TEST Eb Logical Compare", "0xa9": "TEST rAX Logical Compare", "0xa8": "TEST AL Logical Compare", "0xa7": "CMPS ES:[DI] Compare String Operands", "0xa6": "CMPS (ES:)[rDI] Compare String Operands", "0xa5": "MOVS DS:[SI] ES:[DI] Move Data from String to String", "0xa4": "MOVS (DS:)[rSI] (ES:)[rDI] Move Data from String to String", "0xa3": "MOV rAX Ovqp Move", "0xa2": "MOV AL Ob Move", "0xa1": "MOV Ovqp rAX Move", "0xa0": "MOV Ob AL Move", "0xf5": "CMC Complement Carry Flag", "0x7a": "JP Jbs Jump short if parity/parity even (PF=1)", "0xf2": "REPNZ eCX Repeat String Operation Prefix", "0x7c": "JL Jbs Jump short if less/not greater (SF!=OF)", "0x7b": "JNP Jbs Jump short if not parity/parity odd", "0x7e": "JLE Jbs Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))", "0x7d": "JNL Jbs Jump short if not less/greater or equal (SF=OF)", "0x7f": "JNLE Jbs Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))", "0xf0": "LOCK Assert LOCK# Signal Prefix", "0x68": "PUSH Ivs SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0x69": "IMUL Evqp Gvqp Signed Multiply", "0x66": " Operand-size override prefix", "0x67": " Address-size override prefix", "0x64": "FS FS FS segment override prefix", "0x65": "GS GS GS segment override prefix", "0x62": "BOUND Gv SS:[rSP] Check Array Index Against Bounds", "0x63": "ARPL Ew Adjust RPL Field of Segment Selector", "0x60": "PUSHA AX SS:[rSP] Push All General-Purpose Registers", "0x61": "POPA SS:[rSP] DI Pop All General-Purpose Registers", "0xd5": "AAD AL ASCII Adjust AX Before Division", "0xce": "INTO eFlags SS:[rSP] Call to Interrupt Procedure", "0xcd": "INT Ib SS:[rSP] Call to Interrupt Procedure", "0xb8": "MOV Ivqp Zvqp Move", "0xcf": "IRET SS:[rSP] Flags Interrupt Return", "0xca": "RETF Iw Return from procedure", "0xcc": "INT 3 SS:[rSP] Call to Interrupt Procedure", "0xcb": "RETF SS:[rSP] Return from procedure", "0xb0": "MOV Ib Zb Move", "0xf3": "REPZ eCX Repeat String Operation Prefix", "0xe3": "JCXZ Jbs Jump short if eCX register is 0", "0xd6": "SALC Undefined and Reserved; Does not Generate #UD", "0x6f": "OUTS DS:[SI] DX Output String to Port", "0x6d": "INS DX ES:[DI] Input from Port to String", "0x6e": "OUTS (DS):[rSI] DX Output String to Port", "0x6b": "IMUL Evqp Gvqp Signed Multiply", "0x6c": "INS DX (ES:)[rDI] Input from Port to String", "0x6a": "PUSH Ibss SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0x79": "JNS Jbs Jump short if not sign (SF=0)", "0x78": "JS Jbs Jump short if sign (SF=1)", "0x71": "JNO Jbs Jump short if not overflow (OF=0)", "0x70": "JO Jbs Jump short if overflow (OF=1)", "0x73": "JNB Jbs Jump short if not below/above or equal/not carry (CF=0)", "0x72": "JB Jbs Jump short if below/not above or equal/carry (CF=1)", "0x75": "JNZ Jbs Jump short if not zero/not equal (ZF=1)", "0x74": "JZ Jbs Jump short if zero/equal (ZF=0)", "0x77": "JNBE Jbs Jump short if not below or equal/above (CF=0 AND ZF=0)", "0x76": "JBE Jbs Jump short if below or equal/not above (CF=1 AND ZF=1)", "0xc5": "LDS Mp DS Load Far Pointer", "0xc4": "LES Mp ES Load Far Pointer", "0xc7": "MOV Ivds Evqp Move", "0xc6": "MOV Ib Eb Move", "0xc1": "ROL Ib Evqp Rotate", "0x8b": "MOV Evqp Gvqp Move", "0xc3": "RETN SS:[rSP] Return from procedure", "0xc2": "RETN SS:[rSP] Return from procedure", "0x8c": "MOV Sw Mw Move", "0xc9": "LEAVE SS:[rSP] eBP High Level Procedure Exit", "0xc8": "ENTER Iw SS:[rSP] Make Stack Frame for Procedure Parameters", "0xf1": "INT1 Undefined and Reserved; Does not Generate #UD", "0xe9": "JMP Jvds Jump", "0xe8": "CALL Jvds SS:[rSP] Call Procedure", "0xd9": "FLD ESsr ST Load Floating Point Value", "0xf7": "TEST Evqp Logical Compare", "0xd0": "ROL 1 Eb Rotate", "0x9f": "LAHF AH Load Status Flags into AH Register", "0x9e": "SAHF AH Store AH into Flags", "0x9d": "POPF SS:[rSP] Flags Pop Stack into FLAGS Register", "0x08": "OR Gb Eb Logical Inclusive OR", "0x09": "OR Gvqp Evqp Logical Inclusive OR", "0x9a": "CALLF Ap SS:[rSP] Call Procedure", "0xd7": "XLAT (DS:)[rBX+AL] AL Table Look-up Translation", "0x04": "ADD Ib AL Add", "0x05": "ADD Ivds rAX Add", "0x06": "PUSH ES SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0x07": "POP SS:[rSP] ES Pop a Value from the Stack", "0x00": "ADD Gb Eb Add", "0x01": "ADD Gvqp Evqp Add", "0x02": "ADD Eb Gb Add", "0x03": "ADD Evqp Gvqp Add", "0x84": "TEST Eb Logical Compare", "0x85": "TEST Evqp Logical Compare", "0x86": "XCHG Gb Exchange Register/Memory with Register", "0x87": "XCHG Gvqp Exchange Register/Memory with Register", "0x80": "ADD Ib Eb Add", "0x81": "ADD Ivds Evqp Add", "0x82": "ADD Ib Eb Add", "0x83": "ADD Ibs Evqp Add", "0x1f": "POP SS:[rSP] DS Pop a Value from the Stack", "0x1e": "PUSH DS SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0x1d": "SBB Ivds rAX Integer Subtraction with Borrow", "0x1c": "SBB Ib AL Integer Subtraction with Borrow", "0x1b": "SBB Evqp Gvqp Integer Subtraction with Borrow", "0x1a": "SBB Eb Gb Integer Subtraction with Borrow", "0xde": "FIADD Mwi ST Add", "0xd1": "ROL 1 Evqp Rotate", "0xd2": "ROL CL Eb Rotate", "0xd3": "ROL CL Evqp Rotate", "0x9c": "PUSHF Flags SS:[rSP] Push FLAGS Register onto the Stack", "0x9b": "FWAIT Check pending unmasked floating-point exceptions", "0x8d": "LEA M Gvqp Load Effective Address", "0x8e": "MOV Ew Sw Move", "0x8f": "POP SS:[rSP] Ev Pop a Value from the Stack", "0xe0": "LOOPNZ Jbs eCX Decrement count; Jump short if count!=0 and ZF=0", "0xe7": "OUT eAX Ib Output to Port", "0x8a": "MOV Eb Gb Move", "0x19": "SBB Gvqp Evqp Integer Subtraction with Borrow", "0x18": "SBB Gb Eb Integer Subtraction with Borrow", "0x17": "POP SS:[rSP] SS Pop a Value from the Stack", "0x16": "PUSH SS SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0x15": "ADC Ivds rAX Add with Carry", "0x14": "ADC Ib AL Add with Carry", "0x13": "ADC Evqp Gvqp Add with Carry", "0x12": "ADC Eb Gb Add with Carry", "0x11": "ADC Gvqp Evqp Add with Carry", "0x10": "ADC Gb Eb Add with Carry", "0xd8": "FADD Msr ST Add", "0xdb": "FILD Mdi ST Load Integer", "0xdc": "FADD Mdr ST Add", "0xdd": "FLD Mdr ST Load Floating Point Value", "0x99": "CWD AX DX Convert Word to Doubleword", "0xdf": "FILD Mwi ST Load Integer", "0x90": "XCHG Zvqp Exchange Register/Memory with Register", "0x0d": "OR Ivds rAX Logical Inclusive OR", "0x0e": "PUSH CS SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0x0f": "POP SS:[rSP] CS Pop a Value from the Stack", "0x98": "CBW AL AX Convert Byte to Word", "0x0a": "OR Eb Gb Logical Inclusive OR", "0x0b": "OR Evqp Gvqp Logical Inclusive OR", "0x0c": "OR Ib AL Logical Inclusive OR"} \ No newline at end of file diff --git a/refactoring_hacks/twobyte_dict.json b/refactoring_hacks/twobyte_dict.json new file mode 100644 index 0000000..4b02664 --- /dev/null +++ b/refactoring_hacks/twobyte_dict.json @@ -0,0 +1 @@ +{"0xe4": "PMULHUW Qq Pq Multiply Packed Unsigned Integers and Store High Result", "0x3a": "ROUNDPS Wps Vps Round Packed Single-FP Values", "0xfa": "PSUBD Qq Pq Subtract Packed Integers", "0xda": "PMINUB Qq Pq Minimum of Packed Unsigned Byte Integers", "0xec": "PADDSB Qq Pq Add Packed Signed Integers with Signed Saturation", "0x28": "MOVAPS Wps Vps Move Aligned Packed Single-FP Values", "0x29": "MOVAPS Vps Wps Move Aligned Packed Single-FP Values", "0xf8": "PSUBB Qq Pq Subtract Packed Integers", "0xeb": "POR Qq Pq Bitwise Logical OR", "0x22": "MOV Rd Cd Move to/from Control Registers", "0x23": "MOV Rd Dd Move to/from Debug Registers", "0x20": "MOV Cd Rd Move to/from Control Registers", "0x21": "MOV Dd Rd Move to/from Debug Registers", "0x26": "MOV Rd Td Move to/from Test Registers", "0xea": "PMINSW Qq Pq Minimum of Packed Signed Word Integers", "0x24": "MOV Td Rd Move to/from Test Registers", "0xf1": "PSLLW Qq Pq Shift Packed Data Left Logical", "0xdb": "PAND Qd Pq Logical AND", "0xef": "PXOR Qq Pq Logical Exclusive OR", "0xe2": "PSRAD Qq Pq Shift Packed Data Right Arithmetic", "0xee": "PMAXSW Qq Pq Maximum of Packed Signed Word Integers", "0xed": "PADDSW Qq Pq Add Packed Signed Integers with Signed Saturation", "0xdc": "PADDUSB Qq Pq Add Packed Unsigned Integers with Unsigned Saturation", "0x35": "SYSEXIT IA32_SYSENTER_CS SS Fast Return from Fast System Call", "0x34": "SYSENTER IA32_SYSENTER_CS SS Fast System Call", "0x37": "GETSEC EAX GETSEC Leaf Functions", "0x31": "RDTSC IA32_TIME_STAMP_COUNTER EAX Read Time-Stamp Counter", "0x30": "WRMSR rCX MSR Write to Model Specific Register", "0x33": "RDPMC PMC EAX Read Performance-Monitoring Counters", "0x32": "RDMSR rCX rAX Read from Model Specific Register", "0x38": "PSHUFB Qq Pq Packed Shuffle Bytes", "0xc0": "XADD Eb Exchange and Add", "0xe1": "PSRAW Qq Pq Shift Packed Data Right Arithmetic", "0xfe": "PADDD Qq Pq Add Packed Integers", "0x88": "JS Jvds Jump short if sign (SF=1)", "0xdd": "PADDUSW Qq Pq Add Packed Unsigned Integers with Unsigned Saturation", "0x89": "JNS Jvds Jump short if not sign (SF=0)", "0x2b": "MOVNTPS Vps Mps Store Packed Single-FP Values Using Non-Temporal Hint", "0x2c": "CVTTPS2PI Wpsq Ppi Convert with Trunc. Packed Single-FP Values to1.11 PackedDW Integers", "0xfd": "PADDW Qq Pq Add Packed Integers", "0x2a": "CVTPI2PS Qpi Vps Convert Packed DW Integers to1.11 PackedSingle-FP Values", "0x2f": "COMISS Vss Compare Scalar Ordered Single-FP Values and Set EFLAGS", "0xfc": "PADDB Qq Pq Add Packed Integers", "0x2d": "CVTPS2PI Wpsq Ppi Convert Packed Single-FP Values to1.11 PackedDW Integers", "0x2e": "UCOMISS Vss Unordered Compare Scalar Single-FP Values and Set EFLAGS", "0x5c": "SUBPS Wps Vps Subtract Packed Single-FP Values", "0x5b": "CVTDQ2PS Wdq Vps Convert Packed DW Integers to1.11 PackedSingle-FP Values", "0x5a": "CVTPS2PD Wps Vpd Convert Packed Single-FP Values to1.11 PackedDouble-FP Values", "0xba": "BT Evqp Bit Test", "0x5f": "MAXPS Wps Vps Return Maximum Packed Single-FP Values", "0x5e": "DIVPS Wps Vps Divide Packed Single-FP Values", "0x5d": "MINPS Wps Vps Return Minimum Packed Single-FP Values", "0x40": "CMOVO Evqp Gvqp Conditional Move - overflow (OF=1)", "0x41": "CMOVNO Evqp Gvqp Conditional Move - not overflow (OF=0)", "0x42": "CMOVB Evqp Gvqp Conditional Move - below/not above or equal/carry (CF=1)", "0x43": "CMOVNB Evqp Gvqp Conditional Move - not below/above or equal/not carry (CF=0)", "0x44": "CMOVZ Evqp Gvqp Conditional Move - zero/equal (ZF=0)", "0x45": "CMOVNZ Evqp Gvqp Conditional Move - not zero/not equal (ZF=1)", "0x46": "CMOVBE Evqp Gvqp Conditional Move - below or equal/not above (CF=1 AND ZF=1)", "0x47": "CMOVNBE Evqp Gvqp Conditional Move - not below or equal/above (CF=0 AND ZF=0)", "0x48": "CMOVS Evqp Gvqp Conditional Move - sign (SF=1)", "0x49": "CMOVNS Evqp Gvqp Conditional Move - not sign (SF=0)", "0xaf": "IMUL Evqp Gvqp Signed Multiply", "0xae": "FXSAVE ST Mstx Save x87 FPU, MMX, XMM, and MXCSR State", "0xad": "SHRD Gvqp Evqp Double Precision Shift Right", "0xac": "SHRD Gvqp Evqp Double Precision Shift Right", "0xab": "BTS Gvqp Evqp Bit Test and Set", "0xaa": "RSM Flags Resume from System Management Mode", "0xe6": "CVTPD2DQ Wpd Vdq Convert Packed Double-FP Values to1.11 PackedDW Integers", "0x4a": "CMOVP Evqp Gvqp Conditional Move - parity/parity even (PF=1)", "0x4b": "CMOVNP Evqp Gvqp Conditional Move - not parity/parity odd", "0x4c": "CMOVL Evqp Gvqp Conditional Move - less/not greater (SF!=OF)", "0x4d": "CMOVNL Evqp Gvqp Conditional Move - not less/greater or equal (SF=OF)", "0x4e": "CMOVLE Evqp Gvqp Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF))", "0x4f": "CMOVNLE Evqp Gvqp Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF))", "0x53": "RCPPS Wps Vps Compute Reciprocals of Packed Single-FP Values", "0x52": "RSQRTPS Wps Vps Compute Recipr. of Square Roots of Packed Single-FP Values", "0x51": "SQRTPS Wps Vps Compute Square Roots of Packed Single-FP Values", "0x50": "MOVMSKPS Ups Gdqp Extract Packed Single-FP Sign Mask", "0x57": "XORPS Wps Vps Bitwise Logical XOR for Single-FP Values", "0x56": "ORPS Wps Vps Bitwise Logical OR of Single-FP Values", "0x55": "ANDNPS Wps Vps Bitwise Logical AND NOT of Packed Single-FP Values", "0x54": "ANDPS Wps Vps Bitwise Logical AND of Packed Single-FP Values", "0xe5": "PMULHW Qq Pq Multiply Packed Signed Integers and Store High Result", "0x59": "MULPS Wps Vps Multiply Packed Single-FP Values", "0x58": "ADDPS Wps Vps Add Packed Single-FP Values", "0xf4": "PMULUDQ Qq Pq Multiply Packed Unsigned DW Integers", "0xfb": "PSUBQ Qq Pq Subtract Packed Quadword Integers", "0xf9": "PSUBW Qq Pq Subtract Packed Integers", "0xf6": "PSADBW Qq Pq Compute Sum of Absolute Differences", "0xa9": "POP SS:[rSP] GS Pop a Value from the Stack", "0xa8": "PUSH GS SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0xa5": "SHLD Gvqp Evqp Double Precision Shift Left", "0xa4": "SHLD Gvqp Evqp Double Precision Shift Left", "0xa3": "BT Evqp Bit Test", "0xa2": "CPUID IA32_BIOS_SIGN_ID CPU Identification", "0xa1": "POP SS:[rSP] FS Pop a Value from the Stack", "0xa0": "PUSH FS SS:[rSP] Push Word, Doubleword or Quadword Onto the Stack", "0xf5": "PMADDWD Qd Pq Multiply and Add Packed Integers", "0xf2": "PSLLD Qq Pq Shift Packed Data Left Logical", "0x7c": "HADDPD Wpd Vpd Packed Double-FP Horizontal Add", "0xd4": "PADDQ Qq Pq Add Packed Quadword Integers", "0x7e": "MOVD Pq Ed Move Doubleword", "0x7d": "HSUBPD Wpd Vpd Packed Double-FP Horizontal Subtract", "0x7f": "MOVQ Pq Qq Move Quadword", "0xf0": "LDDQU Mdq Vdq Load Unaligned Integer 128 Bits", "0x68": "PUNPCKHBW Qq Pq Unpack High Data", "0x69": "PUNPCKHWD Qq Pq Unpack High Data", "0x66": "PCMPGTD Qd Pq Compare Packed Signed Integers for Greater Than", "0x67": "PACKUSWB Qq Pq Pack with Unsigned Saturation", "0x64": "PCMPGTB Qd Pq Compare Packed Signed Integers for Greater Than", "0x65": "PCMPGTW Qd Pq Compare Packed Signed Integers for Greater Than", "0x62": "PUNPCKLDQ Qd Pq Unpack Low Data", "0x63": "PACKSSWB Qd Pq Pack with Signed Saturation", "0x60": "PUNPCKLBW Qd Pq Unpack Low Data", "0x61": "PUNPCKLWD Qd Pq Unpack Low Data", "0x99": "SETNS Eb Set Byte on Condition - not sign (SF=0)", "0xd5": "PMULLW Qq Pq Multiply Packed Signed Integers and Store Low Result", "0xf3": "PSLLQ Qq Pq Shift Packed Data Left Logical", "0xb8": "JMPE Jump to IA-64 Instruction Set", "0xb9": "UD G Undefined Instruction", "0xb2": "LSS Mptp SS Load Far Pointer", "0xb3": "BTR Gvqp Evqp Bit Test and Reset", "0xb0": "CMPXCHG Gb Eb Compare and Exchange", "0xb1": "CMPXCHG Gvqp Evqp Compare and Exchange", "0xb6": "MOVZX Eb Gvqp Move with Zero-Extend", "0xb7": "MOVZX Ew Gvqp Move with Zero-Extend", "0xb4": "LFS Mptp FS Load Far Pointer", "0xb5": "LGS Mptp GS Load Far Pointer", "0xe3": "PAVGW Qq Pq Average Packed Integers", "0xd6": "MOVQ Vq Wq Move Quadword", "0x6f": "MOVQ Qq Pq Move Quadword", "0x6d": "PUNPCKHQDQ Wdq Vdq Unpack High Data", "0x6e": "MOVD Ed Pq Move Doubleword", "0x6b": "PACKSSDW Qq Pq Pack with Signed Saturation", "0x6c": "PUNPCKLQDQ Wdq Vdq Unpack Low Data", "0x6a": "PUNPCKHDQ Qq Pq Unpack High Data", "0x79": "VMWRITE Gd Write Field to Virtual-Machine Control Structure", "0x78": "VMREAD Gd Ed Read Field from Virtual-Machine Control Structure", "0x71": "PSRLW Ib Nq Shift Packed Data Right Logical", "0x70": "PSHUFW Qq Pq Shuffle Packed Words", "0x73": "PSRLQ Ib Nq Shift Packed Data Right Logical", "0x72": "PSRLD Ib Nq Shift Double Quadword Right Logical", "0x75": "PCMPEQW Qq Pq Compare Packed Data for Equal", "0x74": "PCMPEQB Qq Pq Compare Packed Data for Equal", "0x77": "EMMS Empty MMX Technology State", "0x76": "PCMPEQD Qq Pq Compare Packed Data for Equal", "0xc5": "PEXTRW Nq Gdqp Extract Word", "0xc4": "PINSRW Rdqp Pq Insert Word", "0xc7": "CMPXCHG8B EBX Mq Compare and Exchange Bytes", "0xc6": "SHUFPS Wps Vps Shuffle Packed Single-FP Values", "0xc1": "XADD Evqp Exchange and Add", "0x8b": "JNP Jvds Jump short if not parity/parity odd", "0xc3": "MOVNTI Gdqp Mdqp Store Doubleword Using Non-Temporal Hint", "0xc2": "CMPPS Wps Vps Compare Packed Single-FP Values", "0xbb": "BTC Gvqp Evqp Bit Test and Complement", "0xbc": "BSF Evqp Gvqp Bit Scan Forward", "0x8c": "JL Jvds Jump short if less/not greater (SF!=OF)", "0xbf": "MOVSX Ew Gvqp Move with Sign-Extension", "0xc8": "BSWAP Zvqp Byte Swap", "0xbd": "BSR Evqp Gvqp Bit Scan Reverse", "0xbe": "MOVSX Eb Gvqp Move with Sign-Extension", "0xe9": "PSUBSW Qq Pq Subtract Packed Signed Integers with Signed Saturation", "0xe8": "PSUBSB Qq Pq Subtract Packed Signed Integers with Signed Saturation", "0xd9": "PSUBUSW Qq Pq Subtract Packed Unsigned Integers with Unsigned Saturation", "0xf7": "MASKMOVQ Nq (DS:)[rDI] Store Selected Bytes of Quadword", "0xd0": "ADDSUBPD Wpd Vpd Packed Double-FP Add/Subtract", "0x9f": "SETNLE Eb Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF))", "0x9e": "SETLE Eb Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF))", "0x9d": "SETNL Eb Set Byte on Condition - not less/greater or equal (SF=OF)", "0x08": "INVD Invalidate Internal Caches", "0x09": "WBINVD Write Back and Invalidate Cache", "0x9a": "SETP Eb Set Byte on Condition - parity/parity even (PF=1)", "0xd7": "PMOVMSKB Nq Gdqp Move Byte Mask", "0xd8": "PSUBUSB Qq Pq Subtract Packed Unsigned Integers with Unsigned Saturation", "0x05": "LOADALL AX Load All of the CPU Registers", "0x06": "CLTS CR0 Clear Task-Switched Flag in CR0", "0x07": "LOADALL EAX Load All of the CPU Registers", "0x00": "SLDT LDTR Mw Store Local Descriptor Table Register", "0x01": "SGDT GDTR Ms Store Global Descriptor Table Register", "0x02": "LAR Mw Gvqp Load Access Rights Byte", "0x03": "LSL Mw Gvqp Load Segment Limit", "0x84": "JZ Jvds Jump short if zero/equal (ZF=0)", "0x85": "JNZ Jvds Jump short if not zero/not equal (ZF=1)", "0x86": "JBE Jvds Jump short if below or equal/not above (CF=1 AND ZF=1)", "0x87": "JNBE Jvds Jump short if not below or equal/above (CF=0 AND ZF=0)", "0x80": "JO Jvds Jump short if overflow (OF=1)", "0x81": "JNO Jvds Jump short if not overflow (OF=0)", "0x82": "JB Jvds Jump short if below/not above or equal/carry (CF=1)", "0x83": "JNB Jvds Jump short if not below/above or equal/not carry (CF=0)", "0x1f": "HINT_NOP Ev Hintable NOP", "0x1e": "HINT_NOP Ev Hintable NOP", "0x1d": "HINT_NOP Ev Hintable NOP", "0x1c": "HINT_NOP Ev Hintable NOP", "0x1b": "HINT_NOP Ev Hintable NOP", "0x1a": "HINT_NOP Ev Hintable NOP", "0xde": "PMAXUB Qq Pq Maximum of Packed Unsigned Byte Integers", "0xdf": "PANDN Qq Pq Logical AND NOT", "0xd1": "PSRLW Qq Pq Shift Packed Data Right Logical", "0xd2": "PSRLD Qq Pq Shift Packed Data Right Logical", "0xd3": "PSRLQ Qq Pq Shift Packed Data Right Logical", "0x9c": "SETL Eb Set Byte on Condition - less/not greater (SF!=OF)", "0x9b": "SETNP Eb Set Byte on Condition - not parity/parity odd", "0x8d": "JNL Jvds Jump short if not less/greater or equal (SF=OF)", "0x8e": "JLE Jvds Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF))", "0x8f": "JNLE Jvds Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF))", "0xe0": "PAVGB Qq Pq Average Packed Integers", "0xe7": "MOVNTQ Pq Mq Store of Quadword Using Non-Temporal Hint", "0x8a": "JP Jvds Jump short if parity/parity even (PF=1)", "0x19": "HINT_NOP Ev Hintable NOP", "0x18": "HINT_NOP Ev Hintable NOP", "0x17": "MOVHPS Vq Mq Move High Packed Single-FP Values", "0x16": "MOVLHPS Uq Vq Move Packed Single-FP Values Low to High", "0x15": "UNPCKHPS Wq Vps Unpack and Interleave High Packed Single-FP Values", "0x14": "UNPCKLPS Wq Vps Unpack and Interleave Low Packed Single-FP Values", "0x13": "MOVLPS Vq Mq Move Low Packed Single-FP Values", "0x12": "MOVHLPS Uq Vq Move Packed Single-FP Values High to Low", "0x11": "MOVUPS Vps Wps Move Unaligned Packed Single-FP Values", "0x10": "MOVUPS Wps Vps Move Unaligned Packed Single-FP Values", "0x97": "SETNBE Eb Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0)", "0x96": "SETBE Eb Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1)", "0x95": "SETNZ Eb Set Byte on Condition - not zero/not equal (ZF=1)", "0x94": "SETZ Eb Set Byte on Condition - zero/equal (ZF=0)", "0x93": "SETNB Eb Set Byte on Condition - not below/above or equal/not carry (CF=0)", "0x92": "SETB Eb Set Byte on Condition - below/not above or equal/carry (CF=1)", "0x91": "SETNO Eb Set Byte on Condition - not overflow (OF=0)", "0x90": "SETO Eb Set Byte on Condition - overflow (OF=1)", "0x0d": "NOP Ev No Operation", "0x0b": "UD2 Undefined Instruction", "0x98": "SETS Eb Set Byte on Condition - sign (SF=1)"} \ No newline at end of file diff --git a/refactoring_hacks/x86opcodes.xml b/refactoring_hacks/x86opcodes.xml new file mode 100644 index 0000000..337b0f7 --- /dev/null +++ b/refactoring_hacks/x86opcodes.xml @@ -0,0 +1,15151 @@ + + + + + + + ADDEbGb + genarithbinary + oszapcoszapc + Add + + + + + + ADDEvqpGvqp + genarithbinary + oszapcoszapc + Add + + + + + + ADDGbEb + genarithbinary + oszapcoszapc + Add + + + + + + ADDGvqpEvqp + genarithbinary + oszapcoszapc + Add + + + + + + + ADD + AL + Ib + + genarithbinary + oszapcoszapc + Add + + + + + + ADDrAXIvds + genarithbinary + oszapcoszapc + Add + + + + + + + PUSH + SS:[rSP] + ES + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + POP + ES + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + OREbGb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + OREvqpGvqp + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORGbEb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORGvqpEvqp + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORALIb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORrAXIvds + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + + PUSH + SS:[rSP] + CS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 00 + 00 + + POP + CS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 01 + 01 + + + + 02 + + + + + + + ADCEbGb + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCEvqpGvqp + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCGbEb + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCGvqpEvqp + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCALIb + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCrAXIvds + genarithbinary + coszapcoszapc + Add with Carry + + + + + + + PUSH + SS:[rSP] + SS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + POP + SS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + SBBEbGb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBEvqpGvqp + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBGbEb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBGvqpEvqp + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBALIb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBrAXIvds + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + + PUSH + SS:[rSP] + DS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + POP + DS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + ANDEbGb + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDEvqpGvqp + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDGbEb + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDGvqpEvqp + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDALIb + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDrAXIvds + genlogical + oszapcoszpcaoc + Logical AND + + + + + + + ES + ES + + prefixsegreg + ES segment override prefix + + + 10 + 10 + + prefixbranchcond + (use with any branch instruction is reserved) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + DAA + AL + + genarithdecimal + acoszapcszapco + Decimal Adjust AL after Addition + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + SUBEbGb + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBEvqpGvqp + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBGbEb + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBGvqpEvqp + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBALIb + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBrAXIvds + genarithbinary + oszapcoszapc + Subtract + + + + + + + CS + CS + + prefixsegreg + CS segment override prefix + + + 10 + 10 + NTAKEN + prefixbranchcond + Branch not taken prefix (only with Jcc instructions) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + DAS + AL + + genarithdecimal + acoszapcszapco + Decimal Adjust AL after Subtraction + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + XOREbGb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XOREvqpGvqp + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORGbEb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORGvqpEvqp + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORALIb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORrAXIvds + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + + SS + SS + + prefixsegreg + SS segment override prefix + + + 10 + 10 + + prefixbranchcond + (use with any branch instruction is reserved) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + AAA + AL + AH + + genarithdecimal + aoszapcacoszp + ASCII Adjust After Addition + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + CMPEbGb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPEvqpGvqp + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPGbEb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPGvqpEvqp + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPALIb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPrAXIvds + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + + DS + DS + + prefixsegreg + DS segment override prefix + + + 10 + 10 + TAKEN + prefixbranchcond + Branch taken prefix (only with Jcc instructions) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + AAS + AL + AH + + genarithdecimal + aoszapcacoszp + ASCII Adjust AL After Subtraction + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + INCZv + genarithbinary + oszaposzap + Increment by 1 + + + 10 + REX + prefix + Access to new 8-bit registers + + + + + + 10 + REX.B + prefix + Extension of r/m field, base field, or opcode reg field + + + + + + 10 + REX.X + prefix + Extension of SIB index field + + + + + + 10 + REX.XB + prefix + REX.X and REX.B combination + + + + + + 10 + REX.R + prefix + Extension of ModR/M reg field + + + + + + 10 + REX.RB + prefix + REX.R and REX.B combination + + + + + + 10 + REX.RX + prefix + REX.R and REX.X combination + + + + + + 10 + REX.RXB + prefix + REX.R, REX.X and REX.B combination + + + + + + DECZv + genarithbinary + oszaposzap + Decrement by 1 + + + 10 + REX.W + prefix + 64 Bit Operand Size + + + + + + 10 + REX.WB + prefix + REX.W and REX.B combination + + + + + + 10 + REX.WX + prefix + REX.W and REX.X combination + + + + + + 10 + REX.WXB + prefix + REX.W, REX.X and REX.B combination + + + + + + 10 + REX.WR + prefix + REX.W and REX.R combination + + + + + + 10 + REX.WRB + prefix + REX.W, REX.R and REX.B combination + + + + + + 10 + REX.WRX + prefix + REX.W, REX.R and REX.X combination + + + + + + 10 + REX.WRXB + prefix + REX.W, REX.R, REX.X and REX.B combination + + + + + + + PUSH + SS:[rSP] + Zv + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + PUSH + SS:[rSP] + Zvq + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + + POP + Zv + SS:[rSP] + + genstack + Pop a Value from the Stack + + + 10 + + POP + Zvq + SS:[rSP] + + genstack + Pop a Value from the Stack + + + + + + 01 + + PUSHA + + SS:[rSP] + AX + CX + DX + BX + SP + BP + SI + DI + + genstack + Push All General-Purpose Registers + + + 03 + + + PUSHAD + + SS:[rSP] + EAX + ECX + EDX + EBX + ESP + EBP + ESI + EDI + + genstack + Push All General-Purpose Registers + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 01 + + POPA + + DI + SI + BP + BX + DX + CX + AX + SS:[rSP] + + genstack + Pop All General-Purpose Registers + + + 03 + + + POPAD + + EDI + ESI + EBP + EBX + EDX + ECX + EAX + SS:[rSP] + + genstack + Pop All General-Purpose Registers + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + 01 + + BOUND + SS:[rSP] + Gv + Ma + eFlags + + genbreakstack + i + i + i + Check Array Index Against Bounds + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 02 + ARPLEwGw + system + zz + Adjust RPL Field of Segment Selector + + + 10 + + MOVSXD + Gdqp + + Ed + + genconver + Move with Sign-Extension + + + + + + 03 + + FS + FS + + prefixsegreg + FS segment override prefix + + + 10 + 10 + + prefixbranchcond + (only with Jcc instructions) + + + 10 + 10 + + ALTER + + prefixbranchcond + Alternating branch prefix (only with Jcc instructions) + + + + + + + 03 + + GS + GS + + prefixsegreg + GS segment override prefix + + + 10 + 10 + + prefixbranchcond + (only with Jcc instructions) + + + + + + + prefix + Operand-size override prefix + + + 10 + + sse2 + prefix + Precision-size override prefix + + + + + + + prefix + Address-size override prefix + + + + + + 01 + + PUSH + SS:[rSP] + Ivs + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 01 + + IMUL + Gvqp + Evqp + Ivds + + genarithbinary + oszapcocszap + Signed Multiply + + + + + + 01 + + PUSH + SS:[rSP] + Ibss + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 01 + + IMUL + Gvqp + Evqp + Ibs + + genarithbinary + oszapcocszap + Signed Multiply + + + + + + 01 + + INS + + (ES:)[rDI] + DX + + + INSB + + (ES:)[rDI] + DX + + geninoutstring + d + Input from Port to String + + + + + + 01 + + INS + + ES:[DI] + DX + + + INSW + + ES:[DI] + DX + + geninout + string + d + Input from Port to String + + + 03 + + INS + + (ES:)[rDI] + DX + + + INSD + + (ES:)[rDI] + DX + + geninoutstring + d + Input from Port to String + + + + + + 01 + + OUTS + DX + + (DS):[rSI] + + + OUTSB + DX + + (DS):[rSI] + + geninoutstring + d + Output String to Port + + + + + + 01 + + OUTS + DX + + DS:[SI] + + + OUTSW + DX + + DS:[SI] + + geninoutstring + d + Output String to Port + + + 03 + + OUTS + DX + + (DS:)[rSI] + + + OUTSD + DX + + (DS:)[rSI] + + geninoutstring + d + Output String to Port + + + + + + JOJbs + genbranchcond + o + Jump short if overflow (OF=1) + + + + + + JNOJbs + genbranchcond + o + Jump short if not overflow (OF=0) + + + + + + JBJbs + JNAEJbs + JCJbs + genbranchcond + c + Jump short if below/not above or equal/carry (CF=1) + + + + + + JNBJbs + JAEJbs + JNCJbs + genbranchcond + c + Jump short if not below/above or equal/not carry (CF=0) + + + + + + JZJbs + JEJbs + genbranchcond + z + Jump short if zero/equal (ZF=0) + + + + + + JNZJbs + JNEJbs + genbranchcond + z + Jump short if not zero/not equal (ZF=1) + + + + + + JBEJbs + JNAJbs + genbranchcond + + zc + Jump short if below or equal/not above (CF=1 AND ZF=1) + + + + + + JNBEJbs + JAJbs + genbranchcond + + zc + Jump short if not below or equal/above (CF=0 AND ZF=0) + + + + + + JSJbs + genbranchcond + s + Jump short if sign (SF=1) + + + + + + JNSJbs + genbranchcond + s + Jump short if not sign (SF=0) + + + + + + JPJbs + JPEJbs + genbranchcond + p + Jump short if parity/parity even (PF=1) + + + + + + JNPJbs + JPOJbs + genbranchcond + p + Jump short if not parity/parity odd + + + + + + JLJbs + JNGEJbs + genbranchcond + os + Jump short if less/not greater (SF!=OF) + + + + + + JNLJbs + JGEJbs + genbranchcond + os + Jump short if not less/greater or equal (SF=OF) + + + + + + JLEJbs + JNGJbs + genbranchcond + osz + Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + JNLEJbs + JGJbs + genbranchcond + osz + Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 0 + ADDEbIb + genarithbinary + oszapcoszapc + Add + + + 1 + OREbIb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEbIb + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEbIb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + ANDEbIb + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEbIb + genarithbinary + oszapcoszapc + Subtract + + + 6 + XOREbIb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEbIb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + 0 + ADDEvqpIvds + genarithbinary + oszapcoszapc + Add + + + 1 + OREvqpIvds + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEvqpIvds + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEvqpIvds + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + ANDEvqpIvds + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEvqpIvds + genarithbinary + oszapcoszapc + Subtract + + + 6 + XOREvqpIvds + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEvqpIvds + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + 0 + ADDEbIb + genarithbinary + oszapcoszapc + Add + + + 1 + OREbIb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEbIb + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEbIb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + ANDEbIb + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEbIb + genarithbinary + oszapcoszapc + Subtract + + + 6 + XOREbIb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEbIb + genarithbinary + oszapcoszapc + Compare Two Operands + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 0 + ADDEvqpIbs + genarithbinary + oszapcoszapc + Add + + + 1 + 03 + OREvqpIbs + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEvqpIbs + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEvqpIbs + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + 03 + ANDEvqpIbs + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEvqpIbs + genarithbinary + oszapcoszapc + Subtract + + + 6 + 03 + XOREvqpIbs + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEvqpIbs + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + TESTEbGb + genarithbinary + oszapcoszpcaoc + Logical Compare + + + + + + TESTEvqpGvqp + genarithbinary + oszapcoszpcaoc + Logical Compare + + + + + + XCHGGbEb + gendatamov + Exchange Register/Memory with Register + + + + + + XCHGGvqpEvqp + gendatamov + Exchange Register/Memory with Register + + + + + + MOVEbGb + gendatamov + Move + + + + + + MOVEvqpGvqp + gendatamov + Move + + + + + + MOVGbEb + gendatamov + Move + + + + + + MOVGvqpEvqp + gendatamov + Move + + + + + + + MOV + Mw + Sw + + + MOV + Rvqp + Sw + + gendatamov + Move + + + + + + LEAGvqpM + gendatamov + Load Effective Address + + + + + + + MOV + Sw + Ew + + gendatamov + Move + + + + + + 0 + + POP + Ev + SS:[rSP] + + genstack + Pop a Value from the Stack + + + 0 + 10 + + POP + Evq + SS:[rSP] + + genstack + Pop a Value from the Stack + + + + + + + XCHG + Zvqp + rAX + + gendatamov + Exchange Register/Memory with Register + + + + NOP + + gencontrol + No Operation + + + F3 + 09 + + + NOP + + gencontrol + No Operation + + + F3 + 10 + PAUSE + sse2 + cachect + Spin Loop Hint + + + + + + + CBW + + AX + AL + + genconver + Convert Byte to Word + + + 03 + + CWDE + + EAX + AX + + + genconver + Convert Word to Doubleword + + + 10 + + CBW + + AX + AL + + + CWDE + + EAX + AX + + + + CDQE + RAX + EAX + + + genconver + Convert + + + + + + + + + CWD + + DX + + AX + + genconver + Convert Word to Doubleword + + + 03 + + CDQ + + EDX + + EAX + + genconver + Convert Doubleword to Quadword + + + 10 + + CWD + + DX + + AX + + + CDQ + + EDX + + EAX + + + CQO + RDX + RAX + + genconver + Convert + + + + + + + + + CALLF + SS:[rSP] + Ap + + genbranchstack + Call Procedure + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + + FWAIT + WAIT + x87fpucontrol + 0123 + 0123 + Check pending unmasked floating-point exceptions + + + + prefixx87fpucontrol + 0123 + 0123 + Wait Prefix + + + + + + + PUSHF + SS:[rSP] + Flags + + genstackflgctrl + + Push FLAGS Register onto the Stack + + + 03 + + PUSHFD + SS:[rSP] + EFlags + + genstackflgctrl + + Push eFLAGS Register onto the Stack + + + 10 + + PUSHF + SS:[rSP] + Flags + + + PUSHFQ + SS:[rSP] + RFlags + + genstackflgctrl + + Push rFLAGS Register onto the Stack + + + + + + + POPF + Flags + SS:[rSP] + + genstackflgctrl + + Pop Stack into FLAGS Register + + + 03 + + POPFD + EFlags + SS:[rSP] + + genstackflgctrl + + Pop Stack into eFLAGS Register + + + 10 + + POPF + Flags + SS:[rSP] + + + POPFQ + RFlags + SS:[rSP] + + genstackflgctrl + + Pop Stack into rFLAGS Register + + + + + + + SAHF + AH + + gendatamovflgctrl + szapcszapc + Store AH into Flags + + + + + + + LAHF + AH + + gendatamovflgctrl + szapc + Load Status Flags into AH Register + + + + + + + MOV + AL + Ob + + gendatamov + Move + + + + + + + MOV + rAX + Ovqp + + gendatamov + Move + + + + + + + MOV + Ob + AL + + gendatamov + Move + + + + + + + MOV + Ovqp + rAX + + gendatamov + Move + + + + + + + MOVS + + (ES:)[rDI] + + (DS:)[rSI] + + + MOVSB + + (ES:)[rDI] + + (DS:)[rSI] + + gendatamovstring + d + Move Data from String to String + + + + + + + MOVS + + ES:[DI] + + DS:[SI] + + + MOVSW + + ES:[DI] + + DS:[SI] + + gendatamovstring + d + Move Data from String to String + + + 03 + + MOVS + + (ES:)[rDI] + + (DS:)[rSI] + + + MOVSD + + (ES:)[rDI] + + (DS:)[rSI] + + gendatamovstring + d + Move Data from String to String + + + 10 + + MOVS + + [rDI] + + [rSI] + + + MOVSW + + [rDI] + + [rSI] + + + MOVSD + + [rDI] + + [rSI] + + + MOVSQ + + [rDI] + + [rSI] + + gendatamovstring + d + Move Data from String to String + + + + + + + CMPS + + (ES:)[rDI] + + (DS:)[rSI] + + + CMPSB + + (ES:)[rDI] + + (DS:)[rSI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + + + + + CMPS + + ES:[DI] + + DS:[SI] + + + CMPSW + + ES:[DI] + + DS:[SI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + 03 + + CMPS + + (ES:)[rDI] + + (DS:)[rSI] + + + CMPSD + + (ES:)[rDI] + + (DS:)[rSI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + 10 + + CMPS + + [rDI] + + [rSI] + + + CMPSW + + [rDI] + + [rSI] + + + CMPSD + + [rDI] + + [rSI] + + + CMPSQ + + [rDI] + + [rSI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + + + + TESTALIb + genlogical + oszapcoszpcaoc + Logical Compare + + + + + + TESTrAXIvds + genlogical + oszapcoszpcaoc + Logical Compare + + + + + + + STOS + + (ES:)[rDI] + AL + + + STOSB + + (ES:)[rDI] + AL + + gendatamovstring + d + Store String + + + + + + + STOS + + ES:[DI] + + AX + + + STOSW + + ES:[DI] + + AX + + gendatamovstring + d + Store String + + + 03 + + STOS + + (ES:)[rDI] + eAX + + + STOSD + + (ES:)[rDI] + + EAX + + gendatamovstring + d + Store String + + + 10 + + STOS + + [rDI] + rAX + + + STOSW + + [rDI] + + AX + + + STOSD + + [rDI] + + EAX + + + STOSQ + + [rDI] + RAX + + gendatamovstring + d + Store String + + + + + + + LODS + AL + + (DS:)[rSI] + + + LODSB + AL + + (DS:)[rSI] + + gendatamovstring + d + Load String + + + + + + + LODS + + AX + + DS:[SI] + + + LODSW + + AX + + DS:[SI] + + gendatamovstring + d + Load String + + + 03 + + LODS + eAX + + (DS:)[rSI] + + + LODSD + + EAX + + (DS:)[rSI] + + gendatamovstring + d + Load String + + + 10 + + LODS + rAX + + [rSI] + + + LODSW + + AX + + [rSI] + + + LODSD + + EAX + + [rSI] + + + LODSQ + RAX + + [rSI] + + gendatamovstring + d + Load String + + + + + + + SCAS + + (ES:)[rDI] + AL + + + SCASB + + (ES:)[rDI] + AL + + gen + arithstring + binary + doszapcoszapc + Scan String + + + + + + + SCAS + + ES:[DI] + + AX + + + SCASW + + ES:[DI] + + AX + + gen + arithstring + binary + doszapcoszapc + Scan String + + + 03 + + SCAS + + (ES:)[rDI] + eAX + + + SCASD + + (ES:)[rDI] + + EAX + + gen + arithstring + binary + doszapcoszapc + Scan String + + + 10 + + SCAS + + [rDI] + rAX + + + SCASW + + [rDI] + + AX + + + SCASD + + [rDI] + + EAX + + + SCASQ + + [rDI] + RAX + + gen + arithstring + binary + doszapcoszapc + Scan String + + + + + + MOVZbIb + gendatamov + Move + + + + + + MOVZvqpIvqp + gendatamov + Move + + + + + 01 + + 0 + ROLEbIb + genshftrot + oszapcoszapco + Rotate + + + 1 + ROREbIb + genshftrot + oszapcoszapco + Rotate + + + 2 + RCLEbIb + genshftrot + coszapcoszapco + Rotate + + + 3 + RCREbIb + genshftrot + coszapcoszapco + Rotate + + + 4 + SHLEbIb + SALEbIb + genshftrot + oszapcoszpcoac + Shift + + + 5 + SHREbIb + genshftrot + oszapcoszpcoac + Shift + + + 6 + SALEbIb + SHLEbIb + genshftrot + oszapcoszpcoac + Shift + + + 7 + SAREbIb + genshftrot + oszapcoszpcoa + Shift + + + + + 01 + + 0 + ROLEvqpIb + genshftrot + oszapcoszapco + Rotate + + + 1 + ROREvqpIb + genshftrot + oszapcoszapco + Rotate + + + 2 + RCLEvqpIb + genshftrot + coszapcoszapco + Rotate + + + 3 + RCREvqpIb + genshftrot + coszapcoszapco + Rotate + + + 4 + SHLEvqpIb + SALEvqpIb + genshftrot + oszapcoszpcoac + Shift + + + 5 + SHREvqpIb + genshftrot + oszapcoszpcoac + Shift + + + 6 + SALEvqpIb + SHLEvqpIb + genshftrot + oszapcoszpcoac + Shift + + + 7 + SAREvqpIb + genshftrot + oszapcoszpcoa + Shift + + + + + + + RETN + SS:[rSP] + Iw + + genbranchstack + Return from procedure + + + + + + + RETN + SS:[rSP] + + genbranchstack + Return from procedure + + + + + + + + LES + ES + Gv + Mp + + gen + datamovsegreg + Load Far Pointer + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + + LDS + DS + Gv + Mp + + gen + datamovsegreg + Load Far Pointer + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 0 + MOVEbIb + gendatamov + Move + + + + + + 0 + MOVEvqpIvds + gendatamov + Move + + + + + + + + 01 + + ENTER + SS:[rSP] + eBP + Iw + Ib + + genstack + Make Stack Frame for Procedure Parameters + + + 10 + + ENTER + SS:[rSP] + rBP + Iw + Ib + + genstack + Make Stack Frame for Procedure Parameters + + + + + + + + 01 + + LEAVE + eBP + SS:[rSP] + + genstack + High Level Procedure Exit + + + 10 + + LEAVE + rBP + SS:[rSP] + + genstack + High Level Procedure Exit + + + + + + + RETF + Iw + SS:[rSP] + + genbranchstack + Return from procedure + + + + + + + RETF + SS:[rSP] + + genbranchstack + Return from procedure + + + + + + + INT + SS:[rSP] + 3 + eFlags + + genbreakstack + + iii + Call to Interrupt Procedure + + + + + + + INT + SS:[rSP] + Ib + eFlags + + genbreakstack + + iii + Call to Interrupt Procedure + + + + + + + INTO + SS:[rSP] + eFlags + + genbreakstack + o + i + i + i + Call to Interrupt Procedure + + + + + + + IRET + Flags + SS:[rSP] + + genbreakstack + + Interrupt Return + + + 03 + + IRETD + EFlags + SS:[rSP] + + genbreakstack + + Interrupt Return + + + + IRET + Flags + SS:[rSP] + + + IRETD + EFlags + SS:[rSP] + + + IRETQ + RFlags + SS:[rSP] + + genbreakstack + + Interrupt Return + + + + + + 0 + ROLEb1 + genshftrot + oszapcoszapc + Rotate + + + 1 + ROREb1 + genshftrot + oszapcoszapc + Rotate + + + 2 + RCLEb1 + genshftrot + coszapcoszapc + Rotate + + + 3 + RCREb1 + genshftrot + coszapcoszapc + Rotate + + + 4 + SHLEb1 + SALEb1 + genshftrot + oszapcoszpca + Shift + + + 5 + SHREb1 + genshftrot + oszapcoszpca + Shift + + + 6 + SALEb1 + SHLEb1 + genshftrot + oszapcoszpca + Shift + + + 7 + SAREb1 + genshftrot + oszapcoszpca + Shift + + + + + + 0 + ROLEvqp1 + genshftrot + oszapcoszapc + Rotate + + + 1 + ROREvqp1 + genshftrot + oszapcoszapc + Rotate + + + 2 + RCLEvqp1 + genshftrot + coszapcoszapc + Rotate + + + 3 + RCREvqp1 + genshftrot + coszapcoszapc + Rotate + + + 4 + SHLEvqp1 + SALEvqp1 + genshftrot + oszapcoszpca + Shift + + + 5 + SHREvqp1 + genshftrot + oszapcoszpca + Shift + + + 6 + SALEvqp1 + SHLEvqp1 + genshftrot + oszapcoszpca + Shift + + + 7 + SAREvqp1 + genshftrot + oszapcoszpca + Shift + + + + + + 0 + ROLEbCL + genshftrot + oszapcoszapco + Rotate + + + 1 + ROREbCL + genshftrot + oszapcoszapco + Rotate + + + 2 + RCLEbCL + genshftrot + coszapcoszapco + Rotate + + + 3 + RCREbCL + genshftrot + coszapcoszapco + Rotate + + + 4 + SHLEbCL + SALEbCL + genshftrot + oszapcoszpcoac + Shift + + + 5 + SHREbCL + genshftrot + oszapcoszpcoac + Shift + + + 6 + SALEbCL + SHLEbCL + genshftrot + oszapcoszpcoac + Shift + + + 7 + SAREbCL + genshftrot + oszapcoszpcoa + Shift + + + + + + 0 + ROLEvqpCL + genshftrot + oszapcoszapco + Rotate + + + 1 + ROREvqpCL + genshftrot + oszapcoszapco + Rotate + + + 2 + RCLEvqpCL + genshftrot + coszapcoszapco + Rotate + + + 3 + RCREvqpCL + genshftrot + coszapcoszapco + Rotate + + + 4 + SHLEvqpCL + SALEvqpCL + genshftrot + oszapcoszpcoac + Shift + + + 5 + SHREvqpCL + genshftrot + oszapcoszpcoac + Shift + + + 6 + SALEvqpCL + SHLEvqpCL + genshftrot + oszapcoszpcoac + Shift + + + 7 + SAREvqpCL + genshftrot + oszapcoszpca + Shift + + + + + + 0A + + AAM + AL + AH + + genarithdecimal + oszapcszpoac + ASCII Adjust AX After Multiply + + + + AMX + AL + AH + Ib + + genarithdecimal + oszapcszpoac + Adjust AX After Multiply + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 0A + + AAD + AL + AH + + genarithdecimal + oszapcszpoac + ASCII Adjust AX Before Division + + + + ADX + AL + AH + Ib + + genarithdecimal + oszapcszpoac + Adjust AX Before Division + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 02 + + Undefined and Reserved; Does not Generate #UD + + + 02 + + SALC + AL + + + SETALC + AL + + gendatamov + c + Set AL If Carry + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + XLAT + AL + + (DS:)[rBX+AL] + + + XLATB + AL + + (DS:)[rBX+AL] + + gendatamov + Table Look-up Translation + + + + + + + + 0 + + FADDSTMsr + + + FADDSTEST + + x87fpuarith + 0123 + 1 + 023 + Add + + + + 1 + + FMULSTMsr + + + FMULSTEST + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + + 2 + + FCOM + ST + ESsr + + x87fpucompar + 0123 + 0123 + Compare Real + + + 2 + D1 + + + FCOM + ST + ST1 + + x87fpucompar + 0123 + 0123 + Compare Real + + + + 3 + + FCOMPSTESsr + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + 3 + D9 + + + FCOMP + ST + ST1 + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + + 4 + + FSUBSTMsr + + + FSUBSTEST + + x87fpuarith + 0123 + 1 + 023 + Subtract + + + + 5 + + FSUBRSTMsr + + + FSUBRSTEST + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract + + + + 6 + + FDIVSTMsr + + + FDIVSTEST + + x87fpuarith + 0123 + 1 + 023 + Divide + + + + 7 + + FDIVRSTMsr + + + FDIVRSTEST + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide + + + + + + + + 0 + + + FLDSTESsr + + x87fpudatamov + 0123 + 1 + 023 + Load Floating Point Value + + + + 1 + + + FXCHSTEST + + x87fpudatamov + 0123 + 1 + 023 + Exchange Register Contents + + + 1 + C9 + + + FXCH + ST + ST1 + + x87fpudatamov + 0123 + 1 + 023 + Exchange Register Contents + + + + 2 + + + FSTMsrST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value + + + 2 + D0 + + + FNOP + + x87fpucontrol + 0123 + 0123 + No Operation + + + + 3 + + + FSTPMsrST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + 3 + 02 + + + FSTP1ESTST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + 3 + 03 + + + FSTP1ESTST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + + 4 + + + FLDENVMe + + x87fpucontrol + 0123 + 0123 + Load x87 FPU Environment + + + 4 + E0 + + + FCHSST + + x87fpuarith + 0123 + 1 + 023 + Change Sign + + + 4 + E1 + + + FABSST + + x87fpuarith + 0123 + 1 + 023 + Absolute Value + + + 4 + E4 + + + FTSTST + + x87fpucompar + 0123 + 0123 + Test + + + 4 + E5 + + + FXAMST + + x87fpu + 0123 + 0123 + Examine + + + + 5 + + + FLDCWMw + + x87fpucontrol + 0123 + 0123 + Load x87 FPU Control Word + + + 5 + E8 + + + FLD1ST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant +1.0 + + + 5 + E9 + + + FLDL2TST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant log210 + + + 5 + EA + + + FLDL2EST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant log2e + + + 5 + EB + + + FLDPIST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant π + + + 5 + EC + + + FLDLG2ST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant log102 + + + 5 + ED + + + FLDLN2ST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant loge2 + + + 5 + EE + + + FLDZST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant +0.0 + + + + 6 + + + FNSTENVMe + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Environment + + + 6 + 9B + + + FSTENVMe + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Environment + + + 6 + F0 + + + F2XM1ST + + x87fputrans + 0123 + 1 + 023 + Compute 2x-1 + + + 6 + F1 + + + FYL2X + ST1 + ST + + x87fputrans + 0123 + 1 + 023 + Compute y × log2x and Pop + + + 6 + F2 + + + FPTANST + + x87fputrans + 0123 + 12 + 03 + Partial Tangent + + + 6 + F3 + + + FPATAN + ST1 + ST + + x87fputrans + 0123 + 1 + 023 + Partial Arctangent and Pop + + + 6 + F4 + + + FXTRACTST + + x87fpuarith + 0123 + 1 + 023 + Extract Exponent and Significand + + + 6 + F5 + + + FPREM1 + ST + ST1 + + x87fpuarith + 0123 + 0123 + IEEE Partial Remainder + + + 6 + F6 + + + FDECSTP + + x87fpucontrol + 0123 + 1 + 023 + b + Decrement Stack-Top Pointer + + + 6 + F7 + + + FINCSTP + + x87fpucontrol + 0123 + 1 + 023 + b + Increment Stack-Top Pointer + + + + 7 + + + FNSTCWMw + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Control Word + + + 7 + 9B + + + FSTCWMw + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Control Word + + + 7 + F8 + + + FPREM + ST + ST1 + + x87fpuarith + 0123 + 0123 + Partial Remainder (for compatibility with i8087 and i287) + + + 7 + F9 + + + FYL2XP1 + ST1 + ST + + x87fputrans + 0123 + 1 + 023 + Compute y × log2(x+1) and Pop + + + 7 + FA + + + FSQRTST + + x87fpuarith + 0123 + 1 + 023 + Square Root + + + 7 + FB + + + FSINCOSST + + x87fputrans + 0123 + 12 + 03 + Sine and Cosine + + + 7 + FC + + + FRNDINTST + + x87fpuarith + 0123 + 1 + 023 + Round to Integer + + + 7 + FD + + + FSCALE + ST + ST1 + + x87fpuarith + 0123 + 1 + 023 + Scale + + + 7 + FE + + + FSINST + + x87fputrans + 0123 + 12 + 03 + Sine + + + 7 + FF + + + FCOSST + + x87fputrans + 0123 + 12 + 03 + Cosine + + + + + + + + 0 + + FIADDSTMdi + + x87fpuarith + 0123 + 1 + 023 + Add + + + 0 + 07 + + FCMOVBSTEST + + x87fpudatamov + c + 0123 + 1 + 023 + FP Conditional Move - below (CF=1) + + + + 1 + + FIMULSTMdi + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + 1 + 07 + + FCMOVESTEST + + x87fpudatamov + z + 0123 + 1 + 023 + FP Conditional Move - equal (ZF=1) + + + + 2 + + FICOMSTMdi + + x87fpucompar + 0123 + 0123 + Compare Integer + + + 2 + 07 + + FCMOVBESTEST + + x87fpudatamov + z + 0123 + 1 + 023 + FP Conditional Move - below or equal (CF=1 or ZF=1) + + + + 3 + + FICOMPSTMdi + + x87fpucompar + 0123 + 0123 + Compare Integer and Pop + + + 3 + 07 + + FCMOVUSTEST + + x87fpudatamov + p + 0123 + 1 + 023 + FP Conditional Move - unordered (PF=1) + + + + + 4 + + FISUBSTMdi + + x87fpuarith + 0123 + 1 + 023 + Subtract + + + + + 5 + + FISUBRSTMdi + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract + + + + 5 + E9 + 03 + + FUCOMPP + ST + ST1 + + x87fpucompar + 0123 + 0123 + Unordered Compare Floating Point Values and Pop Twice + + + + + 6 + + FIDIVSTMdi + + x87fpuarith + 0123 + 1 + 023 + Divide + + + + + 7 + + FIDIVRSTMdi + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide + + + + + + + + 0 + + FILDSTMdi + + x87fpudatamov + 0123 + 1 + 023 + Load Integer + + + 0 + 07 + + FCMOVNBSTEST + + x87fpudatamov + c + 0123 + 1 + 023 + FP Conditional Move - not below (CF=0) + + + + 1 + 10 + + FISTTPMdiST + + sse3 + x87fpu + + conver + 0123 + 1 + 023 + b + Store Integer with Truncation and Pop + + + 1 + 07 + + FCMOVNESTEST + + x87fpudatamov + z + 0123 + 1 + 023 + FP Conditional Move - not equal (ZF=0) + + + + 2 + + FISTMdiST + + x87fpudatamov + 0123 + 1 + 023 + Store Integer + + + 2 + 07 + + FCMOVNBESTEST + + x87fpudatamov + z + 0123 + 1 + 023 + FP Conditional Move - below or equal (CF=0 and ZF=0) + + + + 3 + + FISTPMdiST + + x87fpudatamov + 0123 + 1 + 023 + Store Integer and Pop + + + 3 + 07 + + FCMOVNUSTEST + + x87fpudatamov + p + 0123 + 1 + 023 + FP Conditional Move - not unordered (PF=0) + + + + + 4 + E0 + 00 + 00 + + FNENI + + x87fpucontrol + Enable NPX Interrupt + + + + 4 + 9B + E0 + 00 + 00 + + FENI + + x87fpucontrol + Enable NPX Interrupt + + + + + 4 + E0 + 01 + + FNENI + + obsolcontrol + Treated as Integer NOP + + + + 4 + E1 + 00 + 00 + + FNDISI + + x87fpucontrol + Disable NPX Interrupt + + + + 4 + 9B + E1 + 00 + 00 + + FDISI + + x87fpucontrol + Disable NPX Interrupt + + + + + 4 + E1 + 01 + + FNDISI + + obsolcontrol + Treated as Integer NOP + + + + 4 + E2 + + FNCLEX + + x87fpucontrol + 0123 + 0123 + Clear Exceptions + + + + 4 + 9B + E2 + + FCLEX + + x87fpucontrol + 0123 + 0123 + Clear Exceptions + + + + 4 + E3 + + FNINIT + + x87fpucontrol + 0123 + abcd + Initialize Floating-Point Unit + + + + 4 + 9B + E3 + + FINIT + + x87fpucontrol + 0123 + abcd + Initialize Floating-Point Unit + + + + 4 + E4 + 02 + 02 + + FNSETPM + + x87fpucontrol + Set Protected Mode + + + + 4 + 9B + E4 + 02 + 02 + + FSETPM + + x87fpucontrol + Set Protected Mode + + + + + 4 + E4 + 03 + + FNSETPM + + obsolcontrol + Treated as Integer NOP + + + + 5 + + FLDSTMer + + x87fpudatamov + 0123 + 1 + 023 + Load Floating Point Value + + + 5 + 07 + + FUCOMISTEST + + x87fpucompar + ozpc + ozpc + o + 1 + 1 + Unordered Compare Floating Point Values and Set EFLAGS + + + + + 6 + 07 + + FCOMISTEST + + x87fpucompar + ozpc + ozpc + o + 1 + 1 + Compare Floating Point Values and Set EFLAGS + + + + + 7 + + FSTPMerST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + + + + + + 0 + + FADDSTMdr + + x87fpuarith + 0123 + 1 + 023 + Add + + + 0 + + FADDESTST + + x87fpuarith + 0123 + 1 + 023 + Add + + + + 1 + + FMULSTMdr + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + 1 + + FMULESTST + + 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Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + + + 07 + 08 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 0 + 10 + + NOP + Ev + + gen + control + No Operation + + + + 1 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 2 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 3 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 4 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 5 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 6 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 7 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + + + + 03 + + MOV + Rd + Cd + + system + oszapcoszapc + Move to/from Control Registers + + + + 03 + + MOV + Hd + Cd + + system + oszapcoszapc + Move to/from Control Registers + + + + 10 + + MOV + Rq + Cq + + system + oszapcoszapc + Move to/from Control Registers + + + + 10 + + MOV + Hq + Cq + + system + oszapcoszapc + Move to/from Control Registers + + + + + + + + 03 + + MOV + + + Rd + Dd + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + + + Hd + Dd + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Rq + Dq + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Hq + Dq + + system + oszapcoszapc + Move to/from Debug Registers + + + + + + + + 03 + + MOV + Cd + Rd + + system + oszapcoszapc + Move to/from Control Registers + + + 03 + + MOV + Cd + Hd + + system + oszapcoszapc + Move to/from Control Registers + + + 10 + + MOV + Cq + Rq + + system + oszapcoszapc + Move to/from Control Registers + + + 10 + + MOV + Cq + Hq + + system + oszapcoszapc + Move to/from Control Registers + + + + + + + + 03 + + MOV + + + Dd + Rd + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + + + Dq + Hq + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Dq + Rq + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Dq + Hq + + system + oszapcoszapc + Move to/from Debug Registers + + + + + + + + 03 + 04 + + MOV + Rd + Td + + system + oszapcoszapc + Move to/from Test Registers + + + 03 + 04 + + MOV + Hd + Td + + system + oszapcoszapc + Move to/from Test Registers + + + + + + + + + + 03 + 04 + + MOV + Td + Rd + + system + oszapcoszapc + Move to/from Test Registers + + + 03 + 04 + + MOV + Td + Hd + + system + oszapcoszapc + Move to/from Test Registers + + + + + + + + 09 + + MOVAPS + Vps + Wps + + sse1 + simdfp + datamov + Move Aligned Packed Single-FP Values + + + + 66 + 10 + + MOVAPD + Vpd + Wpd + + sse2 + pcksclr + datamov + Move Aligned Packed Double-FP Values + + + + + + 09 + + MOVAPS + Wps + Vps + + sse1 + simdfp + datamov + Move Aligned Packed Single-FP Values + + + + 66 + 10 + + MOVAPD + Wpd + Vpd + + sse2 + pcksclr + datamov + Move Aligned Packed Double-FP Values + + + + + + 09 + + CVTPI2PS + Vps + Qpi + + sse1 + conver + Convert Packed DW Integers to Single-FP Values + + + + F3 + 09 + + CVTSI2SS + Vss + Edqp + + sse1 + conver + Convert DW Integer to Scalar Single-FP Value + + + + 66 + 10 + + CVTPI2PD + Vpd + Qpi + + sse2 + pcksclr + conver + Convert Packed DW Integers to Double-FP Values + + + + F2 + 10 + + CVTSI2SD + Vsd + Edqp + + sse2 + pcksclr + conver + Convert DW Integer to Scalar Double-FP Value + + + + + + 09 + + MOVNTPS + Mps + Vps + + sse1 + cachect + Store Packed Single-FP Values Using Non-Temporal Hint + + + + 66 + 10 + + MOVNTPD + Mpd + Vpd + + sse2 + cachect + Store Packed Double-FP Values Using Non-Temporal Hint + + + + + + 09 + + CVTTPS2PI + Ppi + Wpsq + + sse1 + conver + Convert with Trunc. Packed Single-FP Values to DW Integers + + + + F3 + 09 + + CVTTSS2SI + Gdqp + Wss + + sse1 + conver + Convert with Trunc. Scalar Single-FP Value to DW Integer + + + + 66 + 10 + + CVTTPD2PI + Ppi + Wpd + + sse2 + pcksclr + conver + Convert with Trunc. Packed Double-FP Values to DW Integers + + + + F2 + 10 + + CVTTSD2SI + Gdqp + Wsd + + sse2 + pcksclr + conver + Conv. with Trunc. Scalar Double-FP Value to Signed DW Int + + + + + + 09 + + CVTPS2PI + Ppi + Wpsq + + sse1 + conver + Convert Packed Single-FP Values to DW Integers + + + + F3 + 09 + + CVTSS2SI + Gdqp + Wss + + sse1 + conver + Convert Scalar Single-FP Value to DW Integer + + + + 66 + 10 + + CVTPD2PI + Ppi + Wpd + + sse2 + pcksclr + conver + Convert Packed Double-FP Values to DW Integers + + + + F2 + 10 + + CVTSD2SI + Gdqp + Wsd + + sse2 + pcksclr + conver + Convert Scalar Double-FP Value to DW Integer + + + + + + 09 + + UCOMISS + Vss + Wss + + sse1 + simdfp + compar + zpczpc + Unordered Compare Scalar Single-FP Values and Set EFLAGS + + + + 66 + 10 + + UCOMISD + Vsd + Wsd + + sse2 + pcksclr + compar + zpczpc + Unordered Compare Scalar Double-FP Values and Set EFLAGS + + + + + + 09 + + COMISS + Vss + Wss + + sse1 + simdfp + compar + zpczpc + Compare Scalar Ordered Single-FP Values and Set EFLAGS + + + + 66 + 10 + + COMISD + Vsd + Wsd + + sse2 + pcksclr + compar + zpczpc + Compare Scalar Ordered Double-FP Values and Set EFLAGS + + + + + + 05 + + WRMSR + MSR + rCX + rAX + rDX + + system + Write to Model Specific Register + + + + + + 05 + + RDTSC + EAX + EDX + IA32_TIME_STAMP_COUNTER + + system + Read Time-Stamp Counter + + + + + + 05 + + RDMSR + rAX + rDX + rCX + MSR + + system + Read from Model Specific Register + + + + + + 06 + + RDPMC + EAX + EDX + PMC + + system + Read Performance-Monitoring Counters + + + + + + + + + 08 + + SYSENTER + SS + ESP + IA32_SYSENTER_CS + IA32_SYSENTER_ESP + IA32_SYSENTER_EIP + + system + branch + iii + Fast System Call + + + 10 + + SYSENTER + SS + RSP + IA32_SYSENTER_CS + IA32_SYSENTER_ESP + IA32_SYSENTER_EIP + + system + branch + iii + Fast System Call + + + + + + + + 08 + + SYSEXIT + SS + eSP + IA32_SYSENTER_CS + rCX + rDX + + system + branch + trans + Fast Return from Fast System Call + + + + + + + + 12 + + GETSEC + EAX + + smx + + GETSEC Leaf Functions + + + + + + + + + + + + 00 + 12 + + PSHUFB + Pq + Qq + + ssse3 + simdint + Packed Shuffle Bytes + + + 66 + 00 + 12 + + PSHUFB + Vdq + Wdq + + ssse3 + simdint + Packed Shuffle Bytes + + + + + + 01 + 12 + + PHADDW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Add + + + 66 + 01 + 12 + + PHADDW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Add + + + + + + 02 + 12 + + PHADDD + Pq + Qq + + ssse3 + simdint + Packed Horizontal Add + + + 66 + 02 + 12 + + PHADDD + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Add + + + + + + 03 + 12 + + PHADDSW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Add and Saturate + + + 66 + 03 + 12 + + PHADDSW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Add and Saturate + + + + + + 04 + 12 + + PMADDUBSW + Pq + Qq + + ssse3 + simdint + Multiply and Add Packed Signed and Unsigned Bytes + + + 66 + 04 + 12 + + PMADDUBSW + Vdq + Wdq + + ssse3 + simdint + Multiply and Add Packed Signed and Unsigned Bytes + + + + + + 05 + 12 + + PHSUBW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Subtract + + + 66 + 05 + 12 + + PHSUBW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Subtract + + + + + + 06 + 12 + + PHSUBD + Pq + Qq + + ssse3 + simdint + Packed Horizontal Subtract + + + 66 + 06 + 12 + + PHSUBD + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Subtract + + + + + + 07 + 12 + + PHSUBSW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Subtract and Saturate + + + 66 + 07 + 12 + + PHSUBSW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Subtract and Saturate + + + + + + 08 + 12 + + PSIGNB + Pq + Qq + + ssse3 + simdint + Packed SIGN + + + 66 + 08 + 12 + + PSIGNB + Vdq + Wdq + + ssse3 + simdint + Packed SIGN + + + + + + 09 + 12 + + PSIGNW + Pq + Qq + + ssse3 + simdint + Packed SIGN + + + 66 + 09 + 12 + + PSIGNW + Vdq + Wdq + + ssse3 + simdint + Packed SIGN + + + + + + 0A + 12 + + PSIGND + Pq + Qq + + ssse3 + simdint + Packed SIGN + + + 66 + 0A + 12 + + PSIGND + Vdq + Wdq + + ssse3 + simdint + Packed SIGN + + + + + + 0B + 12 + + PMULHRSW + Pq + Qq + + ssse3 + simdint + Packed Multiply High with Round and Scale + + + 66 + 0B + 12 + + PMULHRSW + Vdq + Wdq + + ssse3 + simdint + Packed Multiply High with Round and Scale + + + + + + 66 + 10 + 12 + + PBLENDVB + Vdq + Wdq + XMM0 + + sse41 + simdint + datamov + + Variable Blend Packed Bytes + + + + + + + 66 + 14 + 12 + + BLENDVPS + Vps + Wps + XMM0 + + sse41 + simdint + datamov + + Variable Blend Packed Single-FP Values + + + + + + + 66 + 15 + 12 + + BLENDVPD + Vpd + Wpd + XMM0 + + sse41 + simdint + datamov + + Variable Blend Packed Double-FP Values + + + + + + + 66 + 17 + 12 + + PTEST + Vdq + Wdq + + sse41 + oszapc + oszapc + osap + + Logical Compare + + + + + + + 1C + 12 + + PABSB + Pq + Qq + + ssse3 + simdint + Packed Absolute Value + + + 66 + 1C + 12 + + PABSB + Vdq + Wdq + + ssse3 + simdint + Packed Absolute Value + + + + + + 1D + 12 + + PABSW + Pq + Qq + + ssse3 + simdint + Packed Absolute Value + + + 66 + 1D + 12 + + PABSW + Vdq + Wdq + + ssse3 + simdint + Packed Absolute Value + + + + + + 1E + 12 + + PABSD + Pq + Qq + + ssse3 + simdint + Packed Absolute Value + + + 66 + 1E + 12 + + PABSD + Vdq + Wdq + + ssse3 + simdint + Packed Absolute Value + + + + + + 66 + 20 + 12 + + PMOVSXBW + Vdq + Mq + + + PMOVSXBW + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 21 + 12 + + PMOVSXBD + Vdq + Md + + + PMOVSXBD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 22 + 12 + + PMOVSXBQ + Vdq + Mw + + + PMOVSXBQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 23 + 12 + + PMOVSXWD + Vdq + Mq + + + PMOVSXWD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 24 + 12 + + PMOVSXWQ + Vdq + Md + + + PMOVSXWQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 25 + 12 + + PMOVSXDQ + Vdq + Mq + + + PMOVSXDQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 28 + 12 + + PMULDQ + Vdq + Wdq + + sse41 + simdint + arith + + Multiply Packed Signed Dword Integers + + + + + + + 66 + 29 + 12 + + PCMPEQQ + Vdq + Wdq + + sse41 + simdint + compar + + Compare Packed Qword Data for Equal + + + + + + + 66 + 2A + 12 + + MOVNTDQA + Vdq + Mdq + + sse41 + cachect + + Load Double Quadword Non-Temporal Aligned Hint + + + + + + + 66 + 2B + 12 + + PACKUSDW + Vdq + Wdq + + sse41 + simdint + conver + + Pack with Unsigned Saturation + + + + + + + 66 + 30 + 12 + + PMOVZXBW + Vdq + Mq + + + PMOVZXBW + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 31 + 12 + + PMOVZXBD + Vdq + Md + + + PMOVZXBD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 32 + 12 + + PMOVZXBQ + Vdq + Mw + + + PMOVZXBQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 33 + 12 + + PMOVZXWD + Vdq + Mq + + + PMOVZXWD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 34 + 12 + + PMOVZXWQ + Vdq + Md + + + PMOVZXWQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 35 + 12 + + PMOVZXDQ + Vdq + Mq + + + PMOVZXDQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 37 + 12 + + PCMPGTQ + Vdq + Wdq + + sse42 + simdint + compar + + Compare Packed Qword Data for Greater Than + Compare packed qwords in xmm2/m128 and xmm1 for greater than + + + + + + + 66 + 38 + 12 + + PMINSB + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Signed Byte Integers + + + + + + + 66 + 39 + 12 + + PMINSD + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Signed Dword Integers + + + + + + + 66 + 3A + 12 + + PMINUW + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Unsigned Word Integers + + + + + + + 66 + 3B + 12 + + PMINUD + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Unsigned Dword Integers + + + + + + + 66 + 3C + 12 + + PMAXSB + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Signed Byte Integers + + + + + + + 66 + 3D + 12 + + PMAXSD + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Signed Dword Integers + + + + + + + 66 + 3E + 12 + + PMAXUW + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Unsigned Word Integers + + + + + + + 66 + 3F + 12 + + PMAXUD + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Unsigned Dword Integers + + + + + + + 66 + 40 + 12 + + PMULLD + Vdq + Wdq + + sse41 + simdint + arith + + Multiply Packed Signed Dword Integers and Store Low Result + + + + + + + 66 + 41 + 12 + + PHMINPOSUW + Vdq + Wdq + + sse41 + simdint + compar + + Packed Horizontal Word Minimum + + + + + + + 66 + 80 + 12 + + INVEPT + Gd + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Derived from EPT + Invalidates EPT-derived entries in the TLBs and paging-structure caches + + + + + 66 + 80 + 12 + + INVEPT + Gq + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Derived from EPT + Invalidates EPT-derived entries in the TLBs and paging-structure caches + + + + + + + 66 + 81 + 12 + + INVVPID + Gd + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Based on VPID + Invalidates entries in the TLBs and paging-structure caches based on VPID + + + + + 66 + 81 + 12 + + INVVPID + Gq + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Based on VPID + Invalidates entries in the TLBs and paging-structure caches based on VPID + + + + + + + F0 + 12 + + MOVBE + Gvqp + Mvqp + + gen + datamov + + Move Data After Swapping Bytes + Reverse byte order in op2 and move to op1 + + + + + F2 + F0 + 12 + + CRC32 + Gdqp + Eb + + sse42 + + Accumulate CRC32 Value + Accumulate CRC32 on r/m8 + + + + + + + F1 + 12 + + MOVBE + Mvqp + Gvqp + + gen + datamov + + Move Data After Swapping Bytes + Reverse byte order in op2 and move to op1 + + + + + F2 + F1 + 12 + + CRC32 + Gdqp + Evqp + + sse42 + + Accumulate CRC32 Value + Accumulate CRC32 on r/m8 + + + + + + + + + + + + 66 + 08 + 12 + + ROUNDPS + Vps + Wps + Ib + + sse41 + simdfp + conver + Round Packed Single-FP Values + + + + + + 66 + 09 + 12 + + ROUNDPD + Vps + Wpd + Ib + + sse41 + simdfp + conver + Round Packed Double-FP Values + + + + + + 66 + 0A + 12 + + ROUNDSS + Vss + Wss + Ib + + sse41 + simdfp + conver + Round Scalar Single-FP Values + + + + + + 66 + 0B + 12 + + ROUNDSD + Vsd + Wsd + Ib + + sse41 + simdfp + conver + Round Scalar Double-FP Values + + + + + + 66 + 0C + 12 + + BLENDPS + Vps + Wps + Ib + + sse41 + simdfp + datamov + + Blend Packed Single-FP Values + + + + + + + 66 + 0D + 12 + + BLENDPD + Vpd + Wpd + Ib + + sse41 + simdfp + datamov + + Blend Packed Double-FP Values + + + + + + + 66 + 0E + 12 + + PBLENDW + Vdq + Wdq + Ib + + sse41 + simdint + datamov + + Blend Packed Words + + + + + + + 0F + 12 + + PALIGNR + Pq + Qq + + ssse3 + simdint + Packed Align Right + + + 66 + 0F + 12 + + PALIGNR + Vdq + Wdq + + ssse3 + simdint + Packed Align Right + + + + + + 66 + 14 + 12 + + PEXTRB + Mb + Vdq + Ib + + + PEXTRB + Rdqp + Vdq + Ib + + sse41 + simdint + datamov + + Extract Byte + + + + + + + 66 + 15 + 12 + + PEXTRW + Mw + Vdq + Ib + + + PEXTRW + Rdqp + Vdq + Ib + + sse41 + simdint + datamov + + Extract Word + + + + + + + 66 + 16 + 12 + + PEXTRD + Ed + Vdq + Ib + + + PEXTRQ + Eqp + Vdq + Ib + + sse41 + simdint + datamov + + Extract Dword/Qword + + + + + + + 66 + 17 + 12 + + + EXTRACTPS + Ed + Vdq + Ib + + sse41 + simdfp + datamov + + Extract Packed Single-FP Value + + + + + + + 66 + 20 + 12 + + PINSRB + Vdq + Mb + Ib + + + + PINSRB + Vdq + Rdqp + Ib + + sse41 + simdint + datamov + Insert Byte + + + + + + 66 + 21 + 12 + + INSERTPS + Vps + Ups + Ib + + + INSERTPS + Vps + Md + Ib + + sse41 + simdfp + datamov + + Insert Packed Single-FP Value + + + + + + + 66 + 22 + 12 + + PINSRD + Vdq + Ed + Ib + + + PINSRQ + Vdq + Eqp + Ib + + sse41 + simdint + datamov + Insert Dword/Qword + + + + + + 66 + 40 + 12 + + DPPS + Vps + Wps + + sse41 + simdfp + arith + + Dot Product of Packed Single-FP Values + + + + + + + 66 + 41 + 12 + + DPPD + Vpd + Wpd + + sse41 + simdfp + arith + + Dot Product of Packed Double-FP Values + + + + + + + 66 + 42 + 12 + + MPSADBW + Vdq + Wdq + Ib + + sse41 + simdint + arith + + Compute Multiple Packed Sums of Absolute Difference + + + + + + + 66 + 60 + 12 + + PCMPESTRM + XMM0 + Vdq + Wdq + Ib + rAX + rDX + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Explicit Length Strings, Return Mask + Perform a packed comparison of string data with + explicit lengths, generating a mask, and storing the result + in XMM0 + + + + + + + 66 + 61 + 12 + + PCMPESTRI + rCX + Vdq + Wdq + Ib + rAX + rDX + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Explicit Length Strings, Return Index + Perform a packed comparison of string data with + explicit lengths, generating an index, and storing the + result in rCX + + + + + + + 66 + 62 + 12 + + PCMPISTRM + XMM0 + Vdq + Wdq + Ib + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Implicit Length Strings, Return Mask + Perform a packed comparison of string data with + implicit lengths, generating a mask, and storing the result + in XMM0 + + + + + + + 66 + 63 + 12 + + PCMPISTRI + rCX + Vdq + Wdq + Ib + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Implicit Length Strings, Return Index + Perform a packed comparison of string data with + implicit lengths, generating an index, and storing the + result in rCX + + + + + + + + + + 07 + CMOVOGvqpEvqp + gendatamov + o + Conditional Move - overflow (OF=1) + + + + + + 07 + CMOVNOGvqpEvqp + gendatamov + o + Conditional Move - not overflow (OF=0) + + + + + + 07 + CMOVBGvqpEvqp + CMOVNAEGvqpEvqp + CMOVCGvqpEvqp + gendatamov + c + Conditional Move - below/not above or equal/carry (CF=1) + + + + + + 07 + CMOVNBGvqpEvqp + CMOVAEGvqpEvqp + CMOVNCGvqpEvqp + gendatamov + c + Conditional Move - not below/above or equal/not carry (CF=0) + + + + + + 07 + CMOVZGvqpEvqp + CMOVEGvqpEvqp + gendatamov + z + Conditional Move - zero/equal (ZF=0) + + + + + + 07 + CMOVNZGvqpEvqp + CMOVNEGvqpEvqp + gendatamov + z + Conditional Move - not zero/not equal (ZF=1) + + + + + + 07 + CMOVBEGvqpEvqp + CMOVNAGvqpEvqp + gendatamov + + zc + Conditional Move - below or equal/not above (CF=1 AND ZF=1) + + + + + + 07 + CMOVNBEGvqpEvqp + CMOVAGvqpEvqp + gendatamov + + zc + Conditional Move - not below or equal/above (CF=0 AND ZF=0) + + + + + + 07 + CMOVSGvqpEvqp + gendatamov + s + Conditional Move - sign (SF=1) + + + + + + 07 + CMOVNSGvqpEvqp + gendatamov + s + Conditional Move - not sign (SF=0) + + + + + + 07 + CMOVPGvqpEvqp + CMOVPEGvqpEvqp + gendatamov + p + Conditional Move - parity/parity even (PF=1) + + + + + + 07 + CMOVNPGvqpEvqp + CMOVPOGvqpEvqp + gendatamov + p + Conditional Move - not parity/parity odd + + + + + + 07 + CMOVLGvqpEvqp + CMOVNGEGvqpEvqp + gendatamov + os + Conditional Move - less/not greater (SF!=OF) + + + + + + 07 + CMOVNLGvqpEvqp + CMOVGEGvqpEvqp + gendatamov + os + Conditional Move - not less/greater or equal (SF=OF) + + + + + + 07 + CMOVLEGvqpEvqp + CMOVNGGvqpEvqp + gendatamov + osz + Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + 07 + CMOVNLEGvqpEvqp + CMOVGGvqpEvqp + gendatamov + osz + Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 09 + + MOVMSKPS + Gdqp + Ups + + sse1 + simdfp + datamov + Extract Packed Single-FP Sign Mask + + + + 66 + 10 + + MOVMSKPD + Gdqp + Upd + + sse2 + pcksclr + datamov + Extract Packed Double-FP Sign Mask + + + + + + 09 + + SQRTPS + Vps + Wps + + sse1 + simdfp + arith + Compute Square Roots of Packed Single-FP Values + + + + F3 + 09 + + SQRTSS + Vss + Wss + + sse1 + simdfp + arith + Compute Square Root of Scalar Single-FP Value + + + + 66 + 10 + + SQRTPD + Vpd + Wpd + + sse2 + pcksclr + arith + Compute Square Roots of Packed Double-FP Values + + + + F2 + 10 + + SQRTSD + Vsd + Wsd + + sse2 + pcksclr + arith + Compute Square Root of Scalar Double-FP Value + + + + + + 09 + + RSQRTPS + Vps + Wps + + sse1 + simdfp + arith + Compute Recipr. of Square Roots of Packed Single-FP Values + + + + F3 + 09 + + RSQRTSS + Vss + Wss + + sse1 + simdfp + arith + Compute Recipr. of Square Root of Scalar Single-FP Value + + + + + + 09 + + RCPPS + Vps + Wps + + sse1 + simdfp + arith + Compute Reciprocals of Packed Single-FP Values + + + + F3 + 09 + + RCPSS + Vss + Wss + + sse1 + simdfp + arith + Compute Reciprocal of Scalar Single-FP Values + + + + + + 09 + + ANDPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical AND of Packed Single-FP Values + + + + 66 + 10 + + ANDPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical AND of Packed Double-FP Values + + + + + + 09 + + ANDNPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical AND NOT of Packed Single-FP Values + + + + 66 + 10 + + ANDNPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical AND NOT of Packed Double-FP Values + + + + + + 09 + + ORPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical OR of Single-FP Values + + + + 66 + 10 + + ORPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical OR of Double-FP Values + + + + + + 09 + + XORPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical XOR for Single-FP Values + + + + 66 + 10 + + XORPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical XOR for Double-FP Values + + + + + + 09 + + ADDPS + Vps + Wps + + sse1 + simdfp + arith + Add Packed Single-FP Values + + + + F3 + 09 + + ADDSS + Vss + Wss + + sse1 + simdfp + arith + Add Scalar Single-FP Values + + + + 66 + 10 + + ADDPD + Vpd + Wpd + + sse2 + pcksclr + arith + Add Packed Double-FP Values + + + + F2 + 10 + + ADDSD + Vsd + Wsd + + sse2 + pcksclr + arith + Add Scalar Double-FP Values + + + + + + 09 + + MULPS + Vps + Wps + + sse1 + simdfp + arith + Multiply Packed Single-FP Values + + + + F3 + 09 + + MULSS + Vss + Wss + + sse1 + simdfp + arith + Multiply Scalar Single-FP Value + + + + 66 + 10 + + MULPD + Vpd + Wpd + + sse2 + pcksclr + arith + Multiply Packed Double-FP Values + + + + F2 + 10 + + MULSD + Vsd + Wsd + + sse2 + pcksclr + arith + Multiply Scalar Double-FP Values + + + + + + 10 + + CVTPS2PD + Vpd + Wps + + sse2 + pcksclr + conver + Convert Packed Single-FP Values to Double-FP Values + + + + 66 + 10 + + CVTPD2PS + Vps + Wpd + + sse2 + pcksclr + conver + Convert Packed Double-FP Values to Single-FP Values + + + + F3 + 10 + + CVTSS2SD + Vsd + Wss + + sse2 + pcksclr + conver + Convert Scalar Single-FP Value to Scalar Double-FP Value + + + + F2 + 10 + + CVTSD2SS + Vss + Wsd + + sse2 + pcksclr + conver + Convert Scalar Double-FP Value to Scalar Single-FP Value + + + + + + 10 + + CVTDQ2PS + Vps + Wdq + + sse2 + pcksp + Convert Packed DW Integers to Single-FP Values + + + + 66 + 10 + + CVTPS2DQ + Vdq + Wps + + sse2 + pcksp + Convert Packed Single-FP Values to DW Integers + + + + F3 + 10 + + CVTTPS2DQ + Vdq + Wps + + sse2 + pcksp + Convert with Trunc. Packed Single-FP Values to DW Integers + + + + + + 09 + + SUBPS + Vps + Wps + + sse1 + simdfp + arith + Subtract Packed Single-FP Values + + + + F3 + 09 + + SUBSS + Vss + Wss + + sse1 + simdfp + arith + Subtract Scalar Single-FP Values + + + + 66 + 10 + + SUBPD + Vpd + Wpd + + sse2 + pcksclr + arith + Subtract Packed Double-FP Values + + + + F2 + 10 + + SUBSD + Vsd + Wsd + + sse2 + pcksclr + arith + Subtract Scalar Double-FP Values + + + + + + 09 + + MINPS + Vps + Wps + + sse1 + simdfp + arith + Return Minimum Packed Single-FP Values + + + + F3 + 09 + + MINSS + Vss + Wss + + sse1 + simdfp + arith + Return Minimum Scalar Single-FP Value + + + + 66 + 10 + + MINPD + Vpd + Wpd + + sse2 + pcksclr + arith + Return Minimum Packed Double-FP Values + + + + F2 + 10 + + MINSD + Vsd + Wsd + + sse2 + pcksclr + arith + Return Minimum Scalar Double-FP Value + + + + + + 09 + + DIVPS + Vps + Wps + + sse1 + simdfp + arith + Divide Packed Single-FP Values + + + + F3 + 09 + + DIVSS + Vss + Wss + + sse1 + simdfp + arith + Divide Scalar Single-FP Values + + + + 66 + 10 + + DIVPD + Vpd + Wpd + + sse2 + pcksclr + arith + Divide Packed Double-FP Values + + + + F2 + 10 + + DIVSD + Vsd + Wsd + + sse2 + pcksclr + arith + Divide Scalar Double-FP Values + + + + + + 09 + + MAXPS + Vps + Wps + + sse1 + simdfp + arith + Return Maximum Packed Single-FP Values + + + + F3 + 09 + + MAXSS + Vss + Wss + + sse1 + simdfp + arith + Return Maximum Scalar Single-FP Value + + + + 66 + 10 + + MAXPD + Vpd + Wpd + + sse2 + pcksclr + arith + Return Maximum Packed Double-FP Values + + + + F2 + 10 + + MAXSD + Vsd + Wsd + + sse2 + pcksclr + arith + Return Maximum Scalar Double-FP Value + + + + + + 06 + + PUNPCKLBW + Pq + Qd + + mmx + unpack + Unpack Low Data + + + 66 + 10 + + PUNPCKLBW + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 06 + + PUNPCKLWD + Pq + Qd + + mmx + unpack + Unpack Low Data + + + 66 + 10 + + PUNPCKLWD + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 06 + + PUNPCKLDQ + Pq + Qd + + mmx + unpack + Unpack Low Data + + + 66 + 10 + + PUNPCKLDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 06 + + PACKSSWB + Pq + Qd + + mmx + conver + Pack with Signed Saturation + + + 66 + 10 + + PACKSSWB + Vdq + Wdq + + sse2 + simdint + conver + Pack with Signed Saturation + + + + + + 06 + + PCMPGTB + Pq + Qd + + mmx + compar + Compare Packed Signed Integers for Greater Than + + + 66 + 10 + + PCMPGTB + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Signed Integers for Greater Than + + + + + + 06 + + PCMPGTW + Pq + Qd + + mmx + compar + Compare Packed Signed Integers for Greater Than + + + 66 + 10 + + PCMPGTW + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Signed Integers for Greater Than + + + + + + 06 + + PCMPGTD + Pq + Qd + + mmx + compar + Compare Packed Signed Integers for Greater Than + + + 66 + 10 + + PCMPGTD + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Signed Integers for Greater Than + + + + + + 06 + + PACKUSWB + Pq + Qq + + mmx + conver + Pack with Unsigned Saturation + + + 66 + 10 + + PACKUSWB + Vdq + Wdq + + sse2 + simdint + conver + Pack with Unsigned Saturation + + + + + + 06 + + PUNPCKHBW + Pq + Qq + + mmx + unpack + Unpack High Data + + + 66 + 10 + + PUNPCKHBW + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + PUNPCKHWD + Pq + Qq + + mmx + unpack + Unpack High Data + + + 66 + 10 + + PUNPCKHWD + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + PUNPCKHDQ + Pq + Qq + + mmx + unpack + Unpack High Data + + + 66 + 10 + + PUNPCKHDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + PACKSSDW + Pq + Qq + + mmx + conver + Pack with Signed Saturation + + + 66 + 10 + + PACKSSDW + Vdq + Wdq + + sse2 + simdint + conver + Pack with Signed Saturation + + + + + + 66 + 10 + + PUNPCKLQDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 66 + 10 + + PUNPCKHQDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + MOVD + Pq + Ed + + mmx + datamov + Move Doubleword + + + + 10 + + MOVD + Pq + Ed + + + MOVQ + Pq + Eqp + + mmx + datamov + Move Doubleword/Quadword + + + + 66 + 10 + + MOVD + Vdq + Ed + + sse2 + simdint + datamov + Move Doubleword + + + + 66 + 10 + + MOVD + Vdq + Ed + + + MOVQ + Vdq + Eqp + + sse2 + simdint + datamov + Move Doubleword/Quadword + + + + + + 06 + + MOVQ + Pq + Qq + + mmx + datamov + Move Quadword + + + + 66 + 10 + + MOVDQA + Vdq + Wdq + + sse2 + simdint + datamov + Move Aligned Double Quadword + + + + F3 + 10 + + MOVDQU + Vdq + Wdq + + sse2 + simdint + datamov + Move Unaligned Double Quadword + + + + + + 09 + + PSHUFW + Pq + Qq + Ib + + sse1 + simdint + Shuffle Packed Words + + + + F2 + 10 + + PSHUFLW + Vdq + Wdq + Ib + + sse2 + simdint + shunpck + Shuffle Packed Low Words + + + + F3 + 10 + + PSHUFHW + Vdq + Wdq + Ib + + sse2 + simdint + shunpck + Shuffle Packed High Words + + + + 66 + 10 + + PSHUFD + Vdq + Wdq + Ib + + sse2 + simdint + shunpck + Shuffle Packed Doublewords + + + + + + 2 + 06 + + PSRLW + Nq + Ib + + mmx + shift + Shift Packed Data Right Logical + + + 2 + 66 + 10 + + PSRLW + Udq + Ib + + sse2 + shift + Shift Packed Data Right Logical + + + + 4 + 06 + + PSRAW + Nq + Ib + + mmx + shift + Shift Packed Data Right Arithmetic + + + 4 + 66 + 10 + + PSRAW + Udq + Ib + + sse2 + shift + Shift Packed Data Right Arithmetic + + + + 6 + 06 + + PSLLW + Nq + Ib + + mmx + shift + Shift Packed Data Left Logical + + + 6 + 66 + 10 + + PSLLW + Udq + Ib + + sse2 + shift + Shift Packed Data Left Logical + + + + + + 2 + 06 + + PSRLD + Nq + Ib + + mmx + shift + Shift Double Quadword Right Logical + + + 2 + 66 + 10 + + PSRLD + Udq + Ib + + sse2 + shift + Shift Double Quadword Right Logical + + + + 4 + 06 + + PSRAD + Nq + Ib + + mmx + shift + Shift Packed Data Right Arithmetic + + + 4 + 66 + 10 + + PSRAD + Udq + Ib + + sse2 + shift + Shift Packed Data Right Arithmetic + + + + 6 + 06 + + PSLLD + Nq + Ib + + mmx + shift + Shift Packed Data Left Logical + + + 6 + 66 + 10 + + PSLLD + Udq + Ib + + sse2 + shift + Shift Packed Data Left Logical + + + + + + 2 + 06 + + PSRLQ + Nq + Ib + + mmx + shift + Shift Packed Data Right Logical + + + 2 + 66 + 10 + + PSRLQ + Udq + Ib + + sse2 + shift + Shift Packed Data Right Logical + + + + + 3 + 66 + 10 + + PSRLDQ + Udq + Ib + + sse2 + simdint + shift + Shift Double Quadword Right Logical + + + + 6 + 06 + + PSLLQ + Nq + Ib + + mmx + shift + Shift Packed Data Left Logical + + + 6 + 66 + 10 + + PSLLQ + Udq + Ib + + sse2 + shift + Shift Packed Data Left Logical + + + + + 7 + 66 + 10 + + PSLLDQ + Udq + Ib + + sse2 + simdint + shift + Shift Double Quadword Left Logical + + + + + + 06 + + PCMPEQB + Pq + Qq + + mmx + compar + Compare Packed Data for Equal + + + + 66 + 10 + + PCMPEQB + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Data for Equal + + + + + + 06 + + PCMPEQW + Pq + Qq + + mmx + compar + Compare Packed Data for Equal + + + + 66 + 10 + + PCMPEQW + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Data for Equal + + + + + + 06 + + PCMPEQD + Pq + Qq + + mmx + compar + Compare Packed Data for Equal + + + + 66 + 10 + + PCMPEQD + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Data for Equal + + + + + + 06 + + EMMS + + mmx + x87fpu + control + Empty MMX Technology State + + + + + + 10 + + VMREAD + Ed + Gd + + vmx + + oszapc + oszapc + + Read Field from Virtual-Machine Control Structure + Reads a specified VMCS field + + + + 10 + + VMREAD + Eq + Gq + + vmx + + oszapc + oszapc + + Read Field from Virtual-Machine Control Structure + Reads a specified VMCS field + + + + + + + 10 + + VMWRITE + Gd + Ed + + vmx + + oszapc + oszapc + + Write Field to Virtual-Machine Control Structure + Writes a specified VMCS field + + + + 10 + + VMWRITE + Gq + Eq + + vmx + + oszapc + oszapc + + Write Field to Virtual-Machine Control Structure + Writes a specified VMCS field + + + + + + + + + 66 + 10 + + HADDPD + Vpd + Wpd + + sse3 + simdfp + arith + Packed Double-FP Horizontal Add + + + + F2 + 10 + + HADDPS + Vps + Wps + + sse3 + simdfp + arith + Packed Single-FP Horizontal Add + + + + + + 66 + 10 + + HSUBPD + Vpd + Wpd + + sse3 + simdfp + arith + Packed Double-FP Horizontal Subtract + + + + + F2 + 10 + + HSUBPS + Vps + Wps + + sse3 + simdfp + arith + Packed Single-FP Horizontal Subtract + + + + + + 06 + + MOVD + Ed + Pq + + mmx + datamov + Move Doubleword + + + + 10 + + MOVD + Ed + Pq + + + MOVQ + Eqp + Pq + + mmx + datamov + Move Doubleword/Quadword + + + + 66 + 10 + + MOVD + Ed + Vdq + + sse2 + simdint + datamov + Move Doubleword + + + + 66 + 10 + + MOVD + Ed + Vdq + + + MOVQ + Eqp + Edq + + sse2 + simdint + datamov + Move Doubleword/Quadword + + + + F3 + 10 + + MOVQ + Vq + Wq + + sse2 + simdint + datamov + Move Quadword + + + + + + 06 + + MOVQ + Qq + Pq + + mmx + datamov + Move Quadword + + + + 66 + 10 + + MOVDQA + Wdq + Vdq + + sse2 + simdint + datamov + Move Aligned Double Quadword + + + + F3 + 10 + + MOVDQU + Wdq + Vdq + + sse2 + simdint + datamov + Move Unaligned Double Quadword + + + + + + 03 + JOJvds + genbranchcond + o + Jump short if overflow (OF=1) + + + + + + 03 + JNOJvds + genbranchcond + o + Jump short if not overflow (OF=0) + + + + + + 03 + JBJvds + JNAEJvds + JCJvds + genbranchcond + c + Jump short if below/not above or equal/carry (CF=1) + + + + + + 03 + JNBJvds + JAEJvds + JNCJvds + genbranchcond + c + Jump short if not below/above or equal/not carry (CF=0) + + + + + + 03 + JZJvds + JEJvds + genbranchcond + z + Jump short if zero/equal (ZF=0) + + + + + + 03 + JNZJvds + JNEJvds + genbranchcond + z + Jump short if not zero/not equal (ZF=1) + + + + + + 03 + JBEJvds + JNAJvds + genbranchcond + + zc + Jump short if below or equal/not above (CF=1 AND ZF=1) + + + + + + 03 + JNBEJvds + JAJvds + genbranchcond + + zc + Jump short if not below or equal/above (CF=0 AND ZF=0) + + + + + + 03 + JSJvds + genbranchcond + s + Jump short if sign (SF=1) + + + + + + 03 + JNSJvds + genbranchcond + s + Jump short if not sign (SF=0) + + + + + + 03 + JPJvds + JPEJvds + genbranchcond + p + Jump short if parity/parity even (PF=1) + + + + + + 03 + JNPJvds + JPOJvds + genbranchcond + p + Jump short if not parity/parity odd + + + + + + 03 + JLJvds + JNGEJvds + genbranchcond + os + Jump short if less/not greater (SF!=OF) + + + + + + 03 + JNLJvds + JGEJvds + genbranchcond + os + Jump short if not less/greater or equal (SF=OF) + + + + + + 03 + JLEJvds + JNGJvds + genbranchcond + osz + Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + 03 + JNLEJvds + JGJvds + genbranchcond + osz + Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 0 + 03 + SETOEb + gendatamov + o + Set Byte on Condition - overflow (OF=1) + + + + + + 0 + 03 + SETNOEb + gendatamov + o + Set Byte on Condition - not overflow (OF=0) + + + + + + 0 + 03 + SETBEb + SETNAEEb + SETCEb + gendatamov + c + Set Byte on Condition - below/not above or equal/carry (CF=1) + + + + + + 0 + 03 + SETNBEb + SETAEEb + SETNCEb + gendatamov + c + Set Byte on Condition - not below/above or equal/not carry (CF=0) + + + + + + 0 + 03 + SETZEb + SETEEb + gendatamov + z + Set Byte on Condition - zero/equal (ZF=0) + + + + + + 0 + 03 + SETNZEb + SETNEEb + gendatamov + z + Set Byte on Condition - not zero/not equal (ZF=1) + + + + + + 0 + 03 + SETBEEb + SETNAEb + gendatamov + + zc + Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1) + + + + + + 0 + 03 + SETNBEEb + SETAEb + gendatamov + + zc + Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0) + + + + + + 0 + 03 + SETSEb + gendatamov + s + Set Byte on Condition - sign (SF=1) + + + + + + 0 + 03 + SETNSEb + gendatamov + s + Set Byte on Condition - not sign (SF=0) + + + + + + 0 + 03 + SETPEb + SETPEEb + gendatamov + p + Set Byte on Condition - parity/parity even (PF=1) + + + + + + 0 + 03 + SETNPEb + SETPOEb + gendatamov + p + Set Byte on Condition - not parity/parity odd + + + + + + 0 + 03 + SETLEb + SETNGEEb + gendatamov + os + Set Byte on Condition - less/not greater (SF!=OF) + + + + + + 0 + 03 + SETNLEb + SETGEEb + gendatamov + os + Set Byte on Condition - not less/greater or equal (SF=OF) + + + + + + 0 + 03 + SETLEEb + SETNGEb + gendatamov + osz + Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + 0 + 03 + SETNLEEb + SETGEb + gendatamov + osz + Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 03 + + PUSH + SS:[rSP] + FS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 03 + + POP + FS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + + + + 04 + + CPUID + IA32_BIOS_SIGN_ID + EAX + ECX + EDX + EBX + + gencontrol + CPU Identification + + + + + + 03 + BTEvqpGvqp + genbit + oszapccoszap + Bit Test + + + + + + 03 + + SHLD + Evqp + Gvqp + Ib + + genshftrot + oszapcoszpcoac + Double Precision Shift Left + + + + + + 03 + + SHLD + Evqp + Gvqp + CL + + genshftrot + oszapcoszpcoac + Double Precision Shift Left + + + + + + + + 03 + + PUSH + SS:[rSP] + GS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 03 + + POP + GS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + + + + 03 + + RSM + Flags + + systembranch + + Resume from System Management Mode + + + + + + 03 + BTSEvqpGvqp + genbit + oszapccoszap + Bit Test and Set + + + + + + 03 + SHRDEvqpGvqpIb + genshftrot + oszapcoszpcoac + Double Precision Shift Right + + + + + + 03 + + SHRD + Evqp + Gvqp + CL + + genshftrot + oszapcoszpcoac + Double Precision Shift Right + + + + + + + + + 0 + 08 + + FXSAVE + Mstx + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + + sm + Save x87 FPU, MMX, XMM, and MXCSR State + + + + 0 + 10 + + FXSAVE + Mstx + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + + sm + Save x87 FPU, MMX, XMM, and MXCSR State + + + + + 1 + 08 + + FXRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + Mstx + + sm + Restore x87 FPU, MMX, XMM, and MXCSR State + + + + 1 + 10 + + FXRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + Mstx + + sm + Restore x87 FPU, MMX, XMM, and MXCSR State + + + + 2 + 09 + + LDMXCSR + Md + + sse1 + mxcsrsm + Load MXCSR Register + + + + 3 + 09 + + STMXCSR + Md + + sse1 + mxcsrsm + Store MXCSR Register State + + + + 4 + 12 + + + XSAVE + M + EDX + EAX + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + + system + + Save Processor Extended States + Save processor extended states to memory. The states are specified by EDX:EAX + + + + 4 + 12 + + + XSAVE + M + EDX + EAX + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + + system + + Save Processor Extended States + Save processor extended states to memory. The states are specified by EDX:EAX + + + + + 5 + 10 + + LFENCE + + sse2 + order + Load Fence + + + 5 + 12 + + + XRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + M + EDX + EAX + + system + + Restore Processor Extended States + Restore processor extended states from memory. The states are specified by EDX:EAX + + + + 5 + 12 + + + XRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + M + EDX + EAX + + system + + Restore Processor Extended States + Restore processor extended states from memory. The states are specified by EDX:EAX + + + + + 6 + 10 + + MFENCE + + sse2 + order + Memory Fence + + + + 7 + 09 + + SFENCE + + sse1 + order + Store Fence + + + 7 + 10 + + CLFLUSH + Mb + + sse2 + cachect + Flush Cache Line + + + + + + 03 + IMULGvqpEvqp + genarithbinary + oszapcocszap + Signed Multiply + + + + + + 04 + + CMPXCHG + Eb + AL + Gb + + gen + datamov + arith + binary + oszapcoszapc + Compare and Exchange + + + + + + 04 + + CMPXCHG + Evqp + rAX + Gvqp + + gen + datamov + arith + binary + oszapcoszapc + Compare and Exchange + + + + + + 03 + + LSS + SS + Gvqp + Mptp + + gen + datamovsegreg + Load Far Pointer + + + + + + 03 + BTREvqpGvqp + genbit + oszapccoszap + Bit Test and Reset + + + + + + + 03 + + LFS + FS + Gvqp + Mptp + + gen + datamovsegreg + Load Far Pointer + + + + + + + 03 + + LGS + GS + Gvqp + Mptp + + gen + datamovsegreg + Load Far Pointer + + + + + + 03 + MOVZXGvqpEb + genconver + Move with Zero-Extend + + + + + + 03 + MOVZXGvqpEw + genconver + Move with Zero-Extend + + + + + + 99 + JMPE + systembranch + Jump to IA-64 Instruction Set + + + + F3 + 12 + + POPCNT + Gvqp + Evqp + + gen + bit + oszapc + osapc + + Bit Population Count + Count the 1s in op2 + + + + + + + 02 + + UD + G + E + + gencontrol + Undefined Instruction + + + + + 03 + + 4 + BTEvqpIb + genbit + oszapccoszap + Bit Test + + + 5 + BTSEvqpIb + genbit + oszapccoszap + Bit Test and Set + + + 6 + BTREvqpIb + genbit + oszapccoszap + Bit Test and Reset + + + 7 + BTCEvqpIb + genbit + oszapccoszap + Bit Test and Complement + + + + + + 03 + BTCEvqpGvqp + genbit + oszapccoszap + Bit Test and Complement + + + + + + 03 + BSFGvqpEvqp + genbit + oszapczosapc + Bit Scan Forward + + + + + + 03 + BSRGvqpEvqp + genbit + oszapczosapc + Bit Scan Reverse + + + + + + 03 + MOVSXGvqpEb + genconver + Move with Sign-Extension + + + + + + 03 + MOVSXGvqpEw + genconver + Move with Sign-Extension + + + + + + 04 + XADDEbGb + gen + datamovarith + binary + oszapcoszapc + Exchange and Add + + + + + + 04 + XADDEvqpGvqp + gen + datamovarith + binary + oszapcoszapc + Exchange and Add + + + + + + + + 09 + + CMPPS + Vps + Wps + Ib + + sse1 + simdfp + compar + Compare Packed Single-FP Values + + + + F3 + 09 + + CMPSS + Vss + Wss + Ib + + sse1 + simdfp + compar + Compare Scalar Single-FP Values + + + + 66 + 10 + + CMPPD + Vpd + Wpd + Ib + + sse2 + pcksclr + compar + Compare Packed Double-FP Values + + + + F2 + 10 + + CMPSD + Vsd + Wsd + Ib + + sse2 + pcksclr + compar + Compare Scalar Double-FP Values + + + + + + + + 10 + + MOVNTI + Mdqp + Gdqp + + sse2 + cachect + Store Doubleword Using Non-Temporal Hint + + + + + + + + + 09 + + PINSRW + Pq + Rdqp + Ib + + + PINSRW + Pq + Mw + Ib + + sse1 + simdint + + Insert Word + + + + 66 + 09 + + PINSRW + Vdq + Rdqp + Ib + + + PINSRW + Vdq + Mw + Ib + + sse1 + simdint + + Insert Word + + + + + + + + + 09 + + PEXTRW + Gdqp + Nq + Ib + + sse1 + simdint + + Extract Word + + + + + 66 + 09 + + PEXTRW + Gdqp + Udq + Ib + + sse1 + simdint + + Extract Word + + + + + + + + 09 + + SHUFPS + Vps + Wps + Ib + + sse1 + simdfp + shunpck + Shuffle Packed Single-FP Values + + + + 66 + 10 + + SHUFPD + Vpd + Wpd + Ib + + sse2 + pcksclr + shunpck + Shuffle Packed Double-FP Values + + + + + + + + 1 + 05 + + CMPXCHG8B + Mq + EAX + EDX + EBX + ECX + + gen + datamovarith + binary + zz + Compare and Exchange Bytes + + + + 1 + 10 + + CMPXCHG8B + Mq + + EAX + EDX + EBX + ECX + + + CMPXCHG16B + Mdq + RAX + RDX + RBX + RCX + + gen + datamovarithbinary + zz + Compare and Exchange Bytes + + + + 6 + 10 + + VMPTRLD + Mq + + vmx + + oszapc + oszapc + + Load Pointer to Virtual-Machine Control Structure + Loads the current VMCS pointer from memory + + + + 66 + 6 + 10 + + VMCLEAR + Mq + + vmx + + oszapc + oszapc + + Clear Virtual-Machine Control Structure + Copy VMCS data to VMCS region in memory + + + + F3 + 6 + 10 + + VMXON + Mq + + vmx + + oszapc + oszapc + + Enter VMX Operation + Enter VMX root operation + + + + + 7 + 10 + + VMPTRST + Mq + + vmx + + oszapc + oszapc + + Store Pointer to Virtual-Machine Control Structure + Stores the current VMCS pointer into memory + + + + + + + + 04 + BSWAPZvqp + gendatamov + Byte Swap + + + + + + 66 + 10 + + ADDSUBPD + Vpd + Wpd + + sse3 + simdfp + arith + Packed Double-FP Add/Subtract + + + + F2 + 10 + + ADDSUBPS + Vps + Wps + + sse3 + simdfp + arith + Packed Single-FP Add/Subtract + + + + + + 06 + + PSRLW + Pq + Qq + + mmx + shift + Shift Packed Data Right Logical + + + 66 + 10 + + PSRLW + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Logical + + + + + + 06 + + PSRLD + Pq + Qq + + mmx + shift + Shift Packed Data Right Logical + + + 66 + 10 + + PSRLD + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Logical + + + + + + 06 + + PSRLQ + Pq + Qq + + mmx + shift + Shift Packed Data Right Logical + + + 66 + 10 + + PSRLQ + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Logical + + + + + + 06 + + PADDQ + Pq + Qq + + sse2 + simdint + arith + Add Packed Quadword Integers + + + + 66 + 10 + + PADDQ + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Quadword Integers + + + + + + 06 + + PMULLW + Pq + Qq + + mmx + arith + Multiply Packed Signed Integers and Store Low Result + + + 66 + 10 + + PMULLW + Vdq + Wdq + + sse2 + simdint + arith + Multiply Packed Signed Integers and Store Low Result + + + + + + 66 + 10 + + MOVQ + Wq + Vq + + sse2 + simdint + datamov + Move Quadword + + + + F3 + 10 + + MOVQ2DQ + Vdq + Nq + + sse2 + simdint + datamov + Move Quadword from MMX Technology to XMM Register + + + + F2 + 10 + + MOVDQ2Q + Pq + Uq + + sse2 + simdint + datamov + Move Quadword from XMM to MMX Technology Register + + + + + + 09 + + PMOVMSKB + Gdqp + Nq + + sse1 + simdint + Move Byte Mask + + + + 66 + 09 + + PMOVMSKB + Gdqp + Udq + + sse1 + simdint + Move Byte Mask + + + + + + 06 + + PSUBUSB + Pq + Qq + + mmx + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + 66 + 10 + + PSUBUSB + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + + + + 06 + + PSUBUSW + Pq + Qq + + mmx + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + 66 + 06 + + PSUBUSW + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + + + + 09 + + PMINUB + Pq + Qq + + sse1 + simdint + Minimum of Packed Unsigned Byte Integers + + + + 66 + 09 + + PMINUB + Vdq + Wdq + + sse1 + simdint + Minimum of Packed Unsigned Byte Integers + + + + + + 06 + + PAND + Pq + Qd + + mmx + logical + Logical AND + + + 66 + 10 + + PAND + Vdq + Wdq + + sse2 + simdint + logical + Logical AND + + + + + + 06 + + PADDUSB + Pq + Qq + + mmx + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + 66 + 10 + + PADDUSB + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + + + + 06 + + PADDUSW + Pq + Qq + + mmx + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + 66 + 10 + + PADDUSW + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + + + + 09 + + PMAXUB + Pq + Qq + + sse1 + simdint + Maximum of Packed Unsigned Byte Integers + + + + 66 + 09 + + PMAXUB + Vdq + Wdq + + sse1 + simdint + Maximum of Packed Unsigned Byte Integers + + + + + + 06 + + PANDN + Pq + Qq + + mmx + logical + Logical AND NOT + + + 66 + 10 + + PANDN + Vdq + Wdq + + sse2 + simdint + logical + Logical AND NOT + + + + + + 09 + + PAVGB + Pq + Qq + + sse1 + simdint + Average Packed Integers + + + + 66 + 09 + + PAVGB + Vdq + Wdq + + sse1 + simdint + Average Packed Integers + + + + + + 06 + + PSRAW + Pq + Qq + + mmx + shift + Shift Packed Data Right Arithmetic + + + 66 + 10 + + PSRAW + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Arithmetic + + + + + + 06 + + PSRAD + Pq + Qq + + mmx + shift + Shift Packed Data Right Arithmetic + + + 66 + 10 + + PSRAD + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Arithmetic + + + + + + 09 + + PAVGW + Pq + Qq + + sse1 + simdint + Average Packed Integers + + + + 66 + 09 + + PAVGW + Vdq + Wdq + + sse1 + simdint + Average Packed Integers + + + + + + 09 + + PMULHUW + Pq + Qq + + sse1 + simdint + Multiply Packed Unsigned Integers and Store High Result + + + + 66 + 09 + + PMULHUW + Vdq + Wdq + + sse1 + simdint + Multiply Packed Unsigned Integers and Store High Result + + + + + + 06 + + PMULHW + Pq + Qq + + mmx + arith + Multiply Packed Signed Integers and Store High Result + + + 66 + 10 + + PMULHW + Vdq + Wdq + + sse2 + simdint + arith + Multiply Packed Signed Integers and Store High Result + + + + + + F2 + 10 + + CVTPD2DQ + Vdq + Wpd + + sse2 + pcksclr + conver + Convert Packed Double-FP Values to DW Integers + + + + 66 + 10 + + CVTTPD2DQ + Vdq + Wpd + + sse2 + pcksclr + conver + Convert with Trunc. Packed Double-FP Values to DW Integers + + + + F3 + 10 + + CVTDQ2PD + Vpd + Wdq + + sse2 + pcksclr + conver + Convert Packed DW Integers to Double-FP Values + + + + + + 09 + + MOVNTQ + Mq + Pq + + sse1 + cachect + Store of Quadword Using Non-Temporal Hint + + + + 66 + 10 + + MOVNTDQ + Mdq + Vdq + + sse2 + cachect + Store Double Quadword Using Non-Temporal Hint + + + + + + 06 + + PSUBSB + Pq + Qq + + mmx + arith + Subtract Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PSUBSB + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Signed Integers with Signed Saturation + + + + + + 06 + + PSUBSW + Pq + Qq + + mmx + arith + Subtract Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PSUBSW + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Signed Integers with Signed Saturation + + + + + + 09 + + PMINSW + Pq + Qq + + sse1 + simdint + Minimum of Packed Signed Word Integers + + + + 66 + 09 + + PMINSW + Vdq + Wdq + + sse1 + simdint + Minimum of Packed Signed Word Integers + + + + + + 06 + + POR + Pq + Qq + + mmx + logical + Bitwise Logical OR + + + 66 + 10 + + POR + Vdq + Wdq + + sse2 + simdint + logical + Bitwise Logical OR + + + + + + 06 + + PADDSB + Pq + Qq + + mmx + arith + Add Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PADDSB + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Signed Integers with Signed Saturation + + + + + + 06 + + PADDSW + Pq + Qq + + mmx + arith + Add Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PADDSW + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Signed Integers with Signed Saturation + + + + + + 09 + + PMAXSW + Pq + Qq + + sse1 + simdint + Maximum of Packed Signed Word Integers + + + + 66 + 09 + + PMAXSW + Vdq + Wdq + + sse1 + simdint + Maximum of Packed Signed Word Integers + + + + + + 06 + + PXOR + Pq + Qq + + mmx + logical + Logical Exclusive OR + + + 66 + 10 + + PXOR + Vdq + Wdq + + sse2 + simdint + logical + Logical Exclusive OR + + + + + + F2 + 10 + + LDDQU + Vdq + Mdq + + sse3 + cachect + Load Unaligned Integer 128 Bits + + + + + + 06 + + PSLLW + Pq + Qq + + mmx + shift + Shift Packed Data Left Logical + + + 66 + 10 + + PSLLW + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Left Logical + + + + + + 06 + + PSLLD + Pq + Qq + + mmx + shift + Shift Packed Data Left Logical + + + 66 + 10 + + PSLLD + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Left Logical + + + + + + 06 + + PSLLQ + Pq + Qq + + mmx + shift + Shift Packed Data Left Logical + + + 66 + 10 + + PSLLQ + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Left Logical + + + + + + 10 + + PMULUDQ + Pq + Qq + + sse2 + simdint + arith + Multiply Packed Unsigned DW Integers + + + + 66 + 10 + + PMULUDQ + Vdq + Wdq + + sse2 + simdint + arith + Multiply Packed Unsigned DW Integers + + + + + + 06 + + PMADDWD + Pq + Qd + + mmx + arith + Multiply and Add Packed Integers + + + 66 + 10 + + PMADDWD + Vdq + Wdq + + sse2 + simdint + arith + Multiply and Add Packed Integers + + + + + + 09 + + PSADBW + Pq + Qq + + sse1 + simdint + Compute Sum of Absolute Differences + + + + 66 + 09 + + PSADBW + Vdq + Wdq + + sse1 + simdint + Compute Sum of Absolute Differences + + + + + + 09 + + MASKMOVQ + (DS:)[rDI] + Pq + Nq + + sse1 + cachect + Store Selected Bytes of Quadword + + + + 66 + 10 + + MASKMOVDQU + (DS:)[rDI] + Vdq + Udq + + sse2 + cachect + Store Selected Bytes of Double Quadword + + + + + + 06 + + PSUBB + Pq + Qq + + mmx + arith + Subtract Packed Integers + + + 66 + 10 + + PSUBB + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Integers + + + + + + 06 + + PSUBW + Pq + Qq + + mmx + arith + Subtract Packed Integers + + + 66 + 10 + + PSUBW + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Integers + + + + + + 06 + + PSUBD + Pq + Qq + + mmx + arith + Subtract Packed Integers + + + 66 + 10 + + PSUBD + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Integers + + + + + + 10 + + PSUBQ + Pq + Qq + + sse2 + simdint + arith + Subtract Packed Quadword Integers + + + + 66 + 10 + + PSUBQ + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Quadword Integers + + + + + + 06 + + PADDB + Pq + Qq + + mmx + arith + Add Packed Integers + + + 66 + 10 + + PADDB + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Integers + + + + + + 06 + + PADDW + Pq + Qq + + mmx + arith + Add Packed Integers + + + 66 + 10 + + PADDW + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Integers + + + + + + 06 + + PADDD + Pq + Qq + + mmx + arith + Add Packed Integers + + + 66 + 10 + + PADDD + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Integers + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/refactoring_hacks/x86reference.xml b/refactoring_hacks/x86reference.xml new file mode 100644 index 0000000..93fc962 --- /dev/null +++ b/refactoring_hacks/x86reference.xml @@ -0,0 +1,15197 @@ + + + + + + + + + + + ADDEbGb + genarithbinary + oszapcoszapc + Add + + + + + + ADDEvqpGvqp + genarithbinary + oszapcoszapc + Add + + + + + + ADDGbEb + genarithbinary + oszapcoszapc + Add + + + + + + ADDGvqpEvqp + genarithbinary + oszapcoszapc + Add + + + + + + + ADD + AL + Ib + + genarithbinary + oszapcoszapc + Add + + + + + + ADDrAXIvds + genarithbinary + oszapcoszapc + Add + + + + + + + PUSH + SS:[rSP] + ES + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + POP + ES + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + OREbGb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + OREvqpGvqp + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORGbEb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORGvqpEvqp + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORALIb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + ORrAXIvds + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + + + + + PUSH + SS:[rSP] + CS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 00 + 00 + + POP + CS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 01 + 01 + + + + 02 + + + + + + + ADCEbGb + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCEvqpGvqp + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCGbEb + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCGvqpEvqp + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCALIb + genarithbinary + coszapcoszapc + Add with Carry + + + + + + ADCrAXIvds + genarithbinary + coszapcoszapc + Add with Carry + + + + + + + PUSH + SS:[rSP] + SS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + POP + SS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + SBBEbGb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBEvqpGvqp + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBGbEb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBGvqpEvqp + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBALIb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + SBBrAXIvds + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + + + + + PUSH + SS:[rSP] + DS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + POP + DS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + ANDEbGb + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDEvqpGvqp + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDGbEb + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDGvqpEvqp + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDALIb + genlogical + oszapcoszpcaoc + Logical AND + + + + + + ANDrAXIvds + genlogical + oszapcoszpcaoc + Logical AND + + + + + + + ES + ES + + prefixsegreg + ES segment override prefix + + + 10 + 10 + + prefixbranchcond + (use with any branch instruction is reserved) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + DAA + AL + + genarithdecimal + acoszapcszapco + Decimal Adjust AL after Addition + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + SUBEbGb + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBEvqpGvqp + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBGbEb + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBGvqpEvqp + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBALIb + genarithbinary + oszapcoszapc + Subtract + + + + + + SUBrAXIvds + genarithbinary + oszapcoszapc + Subtract + + + + + + + CS + CS + + prefixsegreg + CS segment override prefix + + + 10 + 10 + NTAKEN + prefixbranchcond + Branch not taken prefix (only with Jcc instructions) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + DAS + AL + + genarithdecimal + acoszapcszapco + Decimal Adjust AL after Subtraction + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + XOREbGb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XOREvqpGvqp + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORGbEb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORGvqpEvqp + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORALIb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + XORrAXIvds + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + + + + + SS + SS + + prefixsegreg + SS segment override prefix + + + 10 + 10 + + prefixbranchcond + (use with any branch instruction is reserved) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + AAA + AL + AH + + genarithdecimal + aoszapcacoszp + ASCII Adjust After Addition + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + CMPEbGb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPEvqpGvqp + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPGbEb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPGvqpEvqp + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPALIb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + CMPrAXIvds + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + + DS + DS + + prefixsegreg + DS segment override prefix + + + 10 + 10 + TAKEN + prefixbranchcond + Branch taken prefix (only with Jcc instructions) + + + 10 + + prefixsegreg + Null Prefix in 64-bit Mode + + + + + + + AAS + AL + AH + + genarithdecimal + aoszapcacoszp + ASCII Adjust AL After Subtraction + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + INCZv + genarithbinary + oszaposzap + Increment by 1 + + + 10 + REX + prefix + Access to new 8-bit registers + + + + + + 10 + REX.B + prefix + Extension of r/m field, base field, or opcode reg field + + + + + + 10 + REX.X + prefix + Extension of SIB index field + + + + + + 10 + REX.XB + prefix + REX.X and REX.B combination + + + + + + 10 + REX.R + prefix + Extension of ModR/M reg field + + + + + + 10 + REX.RB + prefix + REX.R and REX.B combination + + + + + + 10 + REX.RX + prefix + REX.R and REX.X combination + + + + + + 10 + REX.RXB + prefix + REX.R, REX.X and REX.B combination + + + + + + DECZv + genarithbinary + oszaposzap + Decrement by 1 + + + 10 + REX.W + prefix + 64 Bit Operand Size + + + + + + 10 + REX.WB + prefix + REX.W and REX.B combination + + + + + + 10 + REX.WX + prefix + REX.W and REX.X combination + + + + + + 10 + REX.WXB + prefix + REX.W, REX.X and REX.B combination + + + + + + 10 + REX.WR + prefix + REX.W and REX.R combination + + + + + + 10 + REX.WRB + prefix + REX.W, REX.R and REX.B combination + + + + + + 10 + REX.WRX + prefix + REX.W, REX.R and REX.X combination + + + + + + 10 + REX.WRXB + prefix + REX.W, REX.R, REX.X and REX.B combination + + + + + + + PUSH + SS:[rSP] + Zv + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + 10 + + PUSH + SS:[rSP] + Zvq + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + + POP + Zv + SS:[rSP] + + genstack + Pop a Value from the Stack + + + 10 + + POP + Zvq + SS:[rSP] + + genstack + Pop a Value from the Stack + + + + + + 01 + + PUSHA + + SS:[rSP] + AX + CX + DX + BX + SP + BP + SI + DI + + genstack + Push All General-Purpose Registers + + + 03 + + + PUSHAD + + SS:[rSP] + EAX + ECX + EDX + EBX + ESP + EBP + ESI + EDI + + genstack + Push All General-Purpose Registers + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 01 + + POPA + + DI + SI + BP + BX + DX + CX + AX + SS:[rSP] + + genstack + Pop All General-Purpose Registers + + + 03 + + + POPAD + + EDI + ESI + EBP + EBX + EDX + ECX + EAX + SS:[rSP] + + genstack + Pop All General-Purpose Registers + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + 01 + + BOUND + SS:[rSP] + Gv + Ma + eFlags + + genbreakstack + i + i + i + Check Array Index Against Bounds + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 02 + ARPLEwGw + system + zz + Adjust RPL Field of Segment Selector + + + 10 + + MOVSXD + Gdqp + + Ed + + genconver + Move with Sign-Extension + + + + + + 03 + + FS + FS + + prefixsegreg + FS segment override prefix + + + 10 + 10 + + prefixbranchcond + (only with Jcc instructions) + + + 10 + 10 + + ALTER + + prefixbranchcond + Alternating branch prefix (only with Jcc instructions) + + + + + + + 03 + + GS + GS + + prefixsegreg + GS segment override prefix + + + 10 + 10 + + prefixbranchcond + (only with Jcc instructions) + + + + + + + prefix + Operand-size override prefix + + + 10 + + sse2 + prefix + Precision-size override prefix + + + + + + + prefix + Address-size override prefix + + + + + + 01 + + PUSH + SS:[rSP] + Ivs + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 01 + + IMUL + Gvqp + Evqp + Ivds + + genarithbinary + oszapcocszap + Signed Multiply + + + + + + 01 + + PUSH + SS:[rSP] + Ibss + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 01 + + IMUL + Gvqp + Evqp + Ibs + + genarithbinary + oszapcocszap + Signed Multiply + + + + + + 01 + + INS + + (ES:)[rDI] + DX + + + INSB + + (ES:)[rDI] + DX + + geninoutstring + d + Input from Port to String + + + + + + 01 + + INS + + ES:[DI] + DX + + + INSW + + ES:[DI] + DX + + geninout + string + d + Input from Port to String + + + 03 + + INS + + (ES:)[rDI] + DX + + + INSD + + (ES:)[rDI] + DX + + geninoutstring + d + Input from Port to String + + + + + + 01 + + OUTS + DX + + (DS):[rSI] + + + OUTSB + DX + + (DS):[rSI] + + geninoutstring + d + Output String to Port + + + + + + 01 + + OUTS + DX + + DS:[SI] + + + OUTSW + DX + + DS:[SI] + + geninoutstring + d + Output String to Port + + + 03 + + OUTS + DX + + (DS:)[rSI] + + + OUTSD + DX + + (DS:)[rSI] + + geninoutstring + d + Output String to Port + + + + + + JOJbs + genbranchcond + o + Jump short if overflow (OF=1) + + + + + + JNOJbs + genbranchcond + o + Jump short if not overflow (OF=0) + + + + + + JBJbs + JNAEJbs + JCJbs + genbranchcond + c + Jump short if below/not above or equal/carry (CF=1) + + + + + + JNBJbs + JAEJbs + JNCJbs + genbranchcond + c + Jump short if not below/above or equal/not carry (CF=0) + + + + + + JZJbs + JEJbs + genbranchcond + z + Jump short if zero/equal (ZF=0) + + + + + + JNZJbs + JNEJbs + genbranchcond + z + Jump short if not zero/not equal (ZF=1) + + + + + + JBEJbs + JNAJbs + genbranchcond + + zc + Jump short if below or equal/not above (CF=1 AND ZF=1) + + + + + + JNBEJbs + JAJbs + genbranchcond + + zc + Jump short if not below or equal/above (CF=0 AND ZF=0) + + + + + + JSJbs + genbranchcond + s + Jump short if sign (SF=1) + + + + + + JNSJbs + genbranchcond + s + Jump short if not sign (SF=0) + + + + + + JPJbs + JPEJbs + genbranchcond + p + Jump short if parity/parity even (PF=1) + + + + + + JNPJbs + JPOJbs + genbranchcond + p + Jump short if not parity/parity odd + + + + + + JLJbs + JNGEJbs + genbranchcond + os + Jump short if less/not greater (SF!=OF) + + + + + + JNLJbs + JGEJbs + genbranchcond + os + Jump short if not less/greater or equal (SF=OF) + + + + + + JLEJbs + JNGJbs + genbranchcond + osz + Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + JNLEJbs + JGJbs + genbranchcond + osz + Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 0 + ADDEbIb + genarithbinary + oszapcoszapc + Add + + + 1 + OREbIb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEbIb + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEbIb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + ANDEbIb + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEbIb + genarithbinary + oszapcoszapc + Subtract + + + 6 + XOREbIb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEbIb + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + 0 + ADDEvqpIvds + genarithbinary + oszapcoszapc + Add + + + 1 + OREvqpIvds + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEvqpIvds + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEvqpIvds + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + ANDEvqpIvds + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEvqpIvds + genarithbinary + oszapcoszapc + Subtract + + + 6 + XOREvqpIvds + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEvqpIvds + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + 0 + ADDEbIb + genarithbinary + oszapcoszapc + Add + + + 1 + OREbIb + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEbIb + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEbIb + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + ANDEbIb + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEbIb + genarithbinary + oszapcoszapc + Subtract + + + 6 + XOREbIb + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEbIb + genarithbinary + oszapcoszapc + Compare Two Operands + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + 0 + ADDEvqpIbs + genarithbinary + oszapcoszapc + Add + + + 1 + 03 + OREvqpIbs + genlogical + oszapcoszpcaoc + Logical Inclusive OR + + + 2 + ADCEvqpIbs + genarithbinary + coszapcoszapc + Add with Carry + + + 3 + SBBEvqpIbs + genarithbinary + coszapcoszapc + Integer Subtraction with Borrow + + + 4 + 03 + ANDEvqpIbs + genlogical + oszapcoszpcaoc + Logical AND + + + 5 + SUBEvqpIbs + genarithbinary + oszapcoszapc + Subtract + + + 6 + 03 + XOREvqpIbs + genlogical + oszapcoszpcaoc + Logical Exclusive OR + + + 7 + CMPEvqpIbs + genarithbinary + oszapcoszapc + Compare Two Operands + + + + + + TESTEbGb + genarithbinary + oszapcoszpcaoc + Logical Compare + + + + + + TESTEvqpGvqp + genarithbinary + oszapcoszpcaoc + Logical Compare + + + + + + XCHGGbEb + gendatamov + Exchange Register/Memory with Register + + + + + + XCHGGvqpEvqp + gendatamov + Exchange Register/Memory with Register + + + + + + MOVEbGb + gendatamov + Move + + + + + + MOVEvqpGvqp + gendatamov + Move + + + + + + MOVGbEb + gendatamov + Move + + + + + + MOVGvqpEvqp + gendatamov + Move + + + + + + + MOV + Mw + Sw + + + MOV + Rvqp + Sw + + gendatamov + Move + + + + + + LEAGvqpM + gendatamov + Load Effective Address + + + + + + + MOV + Sw + Ew + + gendatamov + Move + + + + + + 0 + + POP + Ev + SS:[rSP] + + genstack + Pop a Value from the Stack + + + 0 + 10 + + POP + Evq + SS:[rSP] + + genstack + Pop a Value from the Stack + + + + + + + XCHG + Zvqp + rAX + + gendatamov + Exchange Register/Memory with Register + + + + NOP + + gencontrol + No Operation + + + F3 + 09 + + + NOP + + gencontrol + No Operation + + + F3 + 10 + PAUSE + sse2 + cachect + Spin Loop Hint + + + + + + + CBW + + AX + AL + + genconver + Convert Byte to Word + + + 03 + + CWDE + + EAX + AX + + + genconver + Convert Word to Doubleword + + + 10 + + CBW + + AX + AL + + + CWDE + + EAX + AX + + + + CDQE + RAX + EAX + + + genconver + Convert + + + + + + + + + CWD + + DX + + AX + + genconver + Convert Word to Doubleword + + + 03 + + CDQ + + EDX + + EAX + + genconver + Convert Doubleword to Quadword + + + 10 + + CWD + + DX + + AX + + + CDQ + + EDX + + EAX + + + CQO + RDX + RAX + + genconver + Convert + + + + + + + + + CALLF + SS:[rSP] + Ap + + genbranchstack + Call Procedure + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + + FWAIT + WAIT + x87fpucontrol + 0123 + 0123 + Check pending unmasked floating-point exceptions + + + + prefixx87fpucontrol + 0123 + 0123 + Wait Prefix + + + + + + + PUSHF + SS:[rSP] + Flags + + genstackflgctrl + + Push FLAGS Register onto the Stack + + + 03 + + PUSHFD + SS:[rSP] + EFlags + + genstackflgctrl + + Push eFLAGS Register onto the Stack + + + 10 + + PUSHF + SS:[rSP] + Flags + + + PUSHFQ + SS:[rSP] + RFlags + + genstackflgctrl + + Push rFLAGS Register onto the Stack + + + + + + + POPF + Flags + SS:[rSP] + + genstackflgctrl + + Pop Stack into FLAGS Register + + + 03 + + POPFD + EFlags + SS:[rSP] + + genstackflgctrl + + Pop Stack into eFLAGS Register + + + 10 + + POPF + Flags + SS:[rSP] + + + POPFQ + RFlags + SS:[rSP] + + genstackflgctrl + + Pop Stack into rFLAGS Register + + + + + + + SAHF + AH + + gendatamovflgctrl + szapcszapc + Store AH into Flags + + + + + + + LAHF + AH + + gendatamovflgctrl + szapc + Load Status Flags into AH Register + + + + + + + MOV + AL + Ob + + gendatamov + Move + + + + + + + MOV + rAX + Ovqp + + gendatamov + Move + + + + + + + MOV + Ob + AL + + gendatamov + Move + + + + + + + MOV + Ovqp + rAX + + gendatamov + Move + + + + + + + MOVS + + (ES:)[rDI] + + (DS:)[rSI] + + + MOVSB + + (ES:)[rDI] + + (DS:)[rSI] + + gendatamovstring + d + Move Data from String to String + + + + + + + MOVS + + ES:[DI] + + DS:[SI] + + + MOVSW + + ES:[DI] + + DS:[SI] + + gendatamovstring + d + Move Data from String to String + + + 03 + + MOVS + + (ES:)[rDI] + + (DS:)[rSI] + + + MOVSD + + (ES:)[rDI] + + (DS:)[rSI] + + gendatamovstring + d + Move Data from String to String + + + 10 + + MOVS + + [rDI] + + [rSI] + + + MOVSW + + [rDI] + + [rSI] + + + MOVSD + + [rDI] + + [rSI] + + + MOVSQ + + [rDI] + + [rSI] + + gendatamovstring + d + Move Data from String to String + + + + + + + CMPS + + (ES:)[rDI] + + (DS:)[rSI] + + + CMPSB + + (ES:)[rDI] + + (DS:)[rSI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + + + + + CMPS + + ES:[DI] + + DS:[SI] + + + CMPSW + + ES:[DI] + + DS:[SI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + 03 + + CMPS + + (ES:)[rDI] + + (DS:)[rSI] + + + CMPSD + + (ES:)[rDI] + + (DS:)[rSI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + 10 + + CMPS + + [rDI] + + [rSI] + + + CMPSW + + [rDI] + + [rSI] + + + CMPSD + + [rDI] + + [rSI] + + + CMPSQ + + [rDI] + + [rSI] + + gen + arithstring + binary + doszapcoszapc + Compare String Operands + + + + + + TESTALIb + genlogical + oszapcoszpcaoc + Logical Compare + + + + + + TESTrAXIvds + genlogical + oszapcoszpcaoc + Logical Compare + + + + + + + STOS + + (ES:)[rDI] + AL + + + STOSB + + (ES:)[rDI] + AL + + gendatamovstring + d + Store String + + + + + + + STOS + + ES:[DI] + + AX + + + STOSW + + ES:[DI] + + AX + + gendatamovstring + d + Store String + + + 03 + + STOS + + (ES:)[rDI] + eAX + + + STOSD + + (ES:)[rDI] + + EAX + + gendatamovstring + d + Store String + + + 10 + + STOS + + [rDI] + rAX + + + STOSW + + [rDI] + + AX + + + STOSD + + [rDI] + + EAX + + + STOSQ + + [rDI] + RAX + + gendatamovstring + d + Store String + + + + + + + LODS + AL + + (DS:)[rSI] + + + LODSB + AL + + (DS:)[rSI] + + gendatamovstring + d + Load String + + + + + + + LODS + + AX + + DS:[SI] + + + LODSW + + AX + + DS:[SI] + + gendatamovstring + d + Load String + + + 03 + + LODS + eAX + + (DS:)[rSI] + + + LODSD + + EAX + + (DS:)[rSI] + + gendatamovstring + d + Load String + + + 10 + + LODS + rAX + + [rSI] + + + LODSW + + AX + + [rSI] + + + LODSD + + EAX + + [rSI] + + + LODSQ + RAX + + [rSI] + + gendatamovstring + d + Load String + + + + + + + SCAS + + (ES:)[rDI] + AL + + + SCASB + + (ES:)[rDI] + AL + + gen + arithstring + binary + doszapcoszapc + Scan String + + + + + + + SCAS + + ES:[DI] + + AX + + + SCASW + + ES:[DI] + + AX + + gen + arithstring + binary + doszapcoszapc + Scan String + + + 03 + + SCAS + + (ES:)[rDI] + eAX + + + SCASD + + (ES:)[rDI] + + EAX + + gen + arithstring + binary + doszapcoszapc + Scan String + + + 10 + + SCAS + + [rDI] + rAX + + + SCASW + + [rDI] + + AX + + + SCASD + + [rDI] + + EAX + + + SCASQ + + [rDI] + RAX + + gen + arithstring + binary + doszapcoszapc + Scan String + + + + + + MOVZbIb + gendatamov + Move + + + + + + MOVZvqpIvqp + gendatamov + Move + + + + + 01 + + 0 + ROLEbIb + genshftrot + oszapcoszapco + Rotate + + + 1 + ROREbIb + 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AL + + gendatamov + c + Set AL If Carry + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + + XLAT + AL + + (DS:)[rBX+AL] + + + XLATB + AL + + (DS:)[rBX+AL] + + gendatamov + Table Look-up Translation + + + + + + + + 0 + + FADDSTMsr + + + FADDSTEST + + x87fpuarith + 0123 + 1 + 023 + Add + + + + 1 + + FMULSTMsr + + + FMULSTEST + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + + 2 + + FCOM + ST + ESsr + + x87fpucompar + 0123 + 0123 + Compare Real + + + 2 + D1 + + + FCOM + ST + ST1 + + x87fpucompar + 0123 + 0123 + Compare Real + + + + 3 + + FCOMPSTESsr + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + 3 + D9 + + + FCOMP + ST + ST1 + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + + 4 + + FSUBSTMsr + + + FSUBSTEST + + x87fpuarith + 0123 + 1 + 023 + Subtract + + + + 5 + + FSUBRSTMsr + + + FSUBRSTEST + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract + + + + 6 + + FDIVSTMsr + + + FDIVSTEST + + x87fpuarith + 0123 + 1 + 023 + Divide + + + + 7 + + FDIVRSTMsr + + + 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x87fpuarith + 0123 + 1 + 023 + Absolute Value + + + 4 + E4 + + + FTSTST + + x87fpucompar + 0123 + 0123 + Test + + + 4 + E5 + + + FXAMST + + x87fpu + 0123 + 0123 + Examine + + + + 5 + + + FLDCWMw + + x87fpucontrol + 0123 + 0123 + Load x87 FPU Control Word + + + 5 + E8 + + + FLD1ST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant +1.0 + + + 5 + E9 + + + FLDL2TST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant log210 + + + 5 + EA + + + FLDL2EST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant log2e + + + 5 + EB + + + FLDPIST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant π + + + 5 + EC + + + FLDLG2ST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant log102 + + + 5 + ED + + + FLDLN2ST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant loge2 + + + 5 + EE + + + FLDZST + + x87fpuldconst + 0123 + 1 + 023 + Load Constant +0.0 + + + + 6 + + + FNSTENVMe + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Environment + + + 6 + 9B + + + FSTENVMe + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Environment + + + 6 + F0 + + + F2XM1ST + + x87fputrans + 0123 + 1 + 023 + Compute 2x-1 + + + 6 + F1 + + + FYL2X + ST1 + ST + + x87fputrans + 0123 + 1 + 023 + Compute y × log2x and Pop + + + 6 + F2 + + + FPTANST + + x87fputrans + 0123 + 12 + 03 + Partial Tangent + + + 6 + F3 + + + FPATAN + ST1 + ST + + x87fputrans + 0123 + 1 + 023 + Partial Arctangent and Pop + + + 6 + F4 + + + FXTRACTST + + x87fpuarith + 0123 + 1 + 023 + Extract Exponent and Significand + + + 6 + F5 + + + FPREM1 + ST + ST1 + + x87fpuarith + 0123 + 0123 + IEEE Partial Remainder + + + 6 + F6 + + + FDECSTP + + x87fpucontrol + 0123 + 1 + 023 + b + Decrement Stack-Top Pointer + + + 6 + F7 + + + FINCSTP + + x87fpucontrol + 0123 + 1 + 023 + b + Increment Stack-Top Pointer + + + + 7 + + + FNSTCWMw + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Control Word + + + 7 + 9B + + + FSTCWMw + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Control Word + + + 7 + F8 + + + FPREM + ST + ST1 + + x87fpuarith + 0123 + 0123 + Partial Remainder (for compatibility with i8087 and i287) + + + 7 + F9 + + + FYL2XP1 + ST1 + ST + + x87fputrans + 0123 + 1 + 023 + Compute y × log2(x+1) and Pop + + + 7 + FA + + + FSQRTST + + x87fpuarith + 0123 + 1 + 023 + Square Root + + + 7 + FB + + + FSINCOSST + + x87fputrans + 0123 + 12 + 03 + Sine and Cosine + + + 7 + FC + + + FRNDINTST + + x87fpuarith + 0123 + 1 + 023 + Round to Integer + + + 7 + FD + + + FSCALE + ST + ST1 + + x87fpuarith + 0123 + 1 + 023 + Scale + + + 7 + FE + + + FSINST + + x87fputrans + 0123 + 12 + 03 + Sine + + + 7 + FF + + + FCOSST + + x87fputrans + 0123 + 12 + 03 + Cosine + + + + + + + + 0 + + FIADDSTMdi + + x87fpuarith + 0123 + 1 + 023 + Add + + + 0 + 07 + + FCMOVBSTEST + + x87fpudatamov + c + 0123 + 1 + 023 + FP Conditional Move - below (CF=1) + + + + 1 + + FIMULSTMdi + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + 1 + 07 + + FCMOVESTEST + + x87fpudatamov + z + 0123 + 1 + 023 + FP Conditional Move - equal (ZF=1) + + + + 2 + + FICOMSTMdi + + x87fpucompar + 0123 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01 + + FNDISI + + obsolcontrol + Treated as Integer NOP + + + + 4 + E2 + + FNCLEX + + x87fpucontrol + 0123 + 0123 + Clear Exceptions + + + + 4 + 9B + E2 + + FCLEX + + x87fpucontrol + 0123 + 0123 + Clear Exceptions + + + + 4 + E3 + + FNINIT + + x87fpucontrol + 0123 + abcd + Initialize Floating-Point Unit + + + + 4 + 9B + E3 + + FINIT + + x87fpucontrol + 0123 + abcd + Initialize Floating-Point Unit + + + + 4 + E4 + 02 + 02 + + FNSETPM + + x87fpucontrol + Set Protected Mode + + + + 4 + 9B + E4 + 02 + 02 + + FSETPM + + x87fpucontrol + Set Protected Mode + + + + + 4 + E4 + 03 + + FNSETPM + + obsolcontrol + Treated as Integer NOP + + + + 5 + + FLDSTMer + + x87fpudatamov + 0123 + 1 + 023 + Load Floating Point Value + + + 5 + 07 + + FUCOMISTEST + + x87fpucompar + ozpc + ozpc + o + 1 + 1 + Unordered Compare Floating Point Values and Set EFLAGS + + + + + 6 + 07 + + FCOMISTEST + + x87fpucompar + ozpc + ozpc + o + 1 + 1 + Compare Floating Point Values and Set EFLAGS + + + + + 7 + + FSTPMerST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + + + + + + 0 + + FADDSTMdr + + x87fpuarith + 0123 + 1 + 023 + Add + + + 0 + + FADDESTST + + x87fpuarith + 0123 + 1 + 023 + Add + + + + 1 + + FMULSTMdr + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + 1 + + FMULESTST + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + + 2 + + FCOMSTMdr + + x87fpucompar + 0123 + 0123 + Compare Real + + + 2 + 02 + + FCOM2STEST + + x87fpucompar + 0123 + 0123 + Compare Real + + + 2 + 03 + + FCOM2STEST + + x87fpucompar + 0123 + 0123 + Compare Real + + + + 3 + + FCOMPSTMdr + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + 3 + 02 + + FCOMP3STEST + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + 3 + 03 + + FCOMP3STEST + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + + 4 + + FSUBSTMdr + + x87fpuarith + 0123 + 1 + 023 + Subtract + + + 4 + + FSUBRESTST + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract + + + + 5 + + FSUBRSTMdr + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract + + + 5 + + FSUBESTST + + x87fpuarith + 0123 + 1 + 023 + Subtract + + + + 6 + + FDIVSTMdr + + x87fpuarith + 0123 + 1 + 023 + Divide + + + 6 + + FDIVRESTST + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide + + + + 7 + + FDIVRSTMdr + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide + + + 7 + + FDIVESTST + + x87fpuarith + 0123 + 1 + 023 + Divide and Pop + + + + + + + + 0 + + FLDSTMdr + + x87fpudatamov + 0123 + 1 + 023 + Load Floating Point Value + + + 0 + + FFREEEST + + x87fpucontrol + 0123 + 0123 + Free Floating-Point Register + + + + 1 + 10 + + FISTTPMqiST + + sse3 + x87fpu + + conver + 0123 + 1 + 023 + b + Store Integer with Truncation and Pop + + + 1 + 02 + + FXCH4STEST + + x87fpudatamov + 0123 + 1 + 023 + Exchange Register Contents + + + 1 + 03 + + FXCH4STEST + + x87fpudatamov + 0123 + 1 + 023 + Exchange Register Contents + + + + 2 + + FSTMdrST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value + + + 2 + + FSTSTEST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value + + + + 3 + + FSTPMdrST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + 3 + + FSTPSTEST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + + 4 + + FRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + Mst + + x87fpucontrol + 0123 + 0123 + Restore x87 FPU State + + + 4 + 03 + + FUCOMSTEST + + x87fpucompar + 0123 + 0123 + Unordered Compare Floating Point Values + + + + 4 + E1 + 03 + + FUCOM + ST + ST1 + + x87fpucompar + 0123 + 0123 + Unordered Compare Floating Point Values + + + + + 5 + 03 + + FUCOMPSTEST + + x87fpucompar + 0123 + 0123 + Unordered Compare Floating Point Values and Pop + + + + 5 + E9 + 03 + + FUCOMP + ST + ST1 + + x87fpucompar + 0123 + 0123 + Unordered Compare Floating Point Values and Pop + + + + + 6 + + FNSAVE + Mst + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + + x87fpucontrol + 0123 + 0123 + abcd + Store x87 FPU State + + + + 6 + 9B + + FSAVE + Mst + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + + x87fpucontrol + 0123 + 0123 + abcd + Store x87 FPU State + + + + + 7 + + FNSTSWMw + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Status Word + + + + 7 + 9B + + FSTSWMw + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Status Word + + + + + + + + 0 + + FIADDSTMwi + + x87fpuarith + 0123 + 1 + 023 + Add + + + 0 + + FADDPESTST + + x87fpuarith + 0123 + 1 + 023 + Add and Pop + + + + 0 + C1 + + FADDP + ST1 + ST + + x87fpuarith + 0123 + 1 + 023 + Add and Pop + + + + 1 + + FIMULSTMwi + + x87fpuarith + 0123 + 1 + 023 + Multiply + + + 1 + + FMULPESTST + + x87fpuarith + 0123 + 1 + 023 + Multiply and Pop + + + + 1 + C9 + + FMULP + ST1 + ST + + x87fpuarith + 0123 + 1 + 023 + Multiply and Pop + + + + 2 + + FICOMSTMwi + + x87fpucompar + 0123 + 0123 + Compare Integer + + + 2 + 02 + + FCOMP5STEST + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + 2 + 03 + + FCOMP5STEST + + x87fpucompar + 0123 + 0123 + Compare Real and Pop + + + + + + 3 + + FICOMPSTMwi + + x87fpucompar + 0123 + 0123 + Compare Integer and Pop + + + + 3 + D9 + + FCOMPP + ST + ST1 + + x87fpucompar + 0123 + 0123 + Compare Real and Pop Twice + + + + 4 + + FISUBSTMwi + + x87fpuarith + 0123 + 1 + 023 + Subtract + + + 4 + + FSUBRPESTST + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract and Pop + + + + 4 + E1 + + FSUBRP + ST1 + ST + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract and Pop + + + + 5 + + FISUBRSTMwi + + x87fpuarith + 0123 + 1 + 023 + Reverse Subtract + + + 5 + + FSUBPESTST + + x87fpuarith + 0123 + 1 + 023 + Subtract and Pop + + + + 5 + E9 + + FSUBP + ST1 + ST + + x87fpuarith + 0123 + 1 + 023 + Subtract and Pop + + + + 6 + + FIDIVSTMwi + + x87fpuarith + 0123 + 1 + 023 + Divide + + + 6 + + FDIVRPESTST + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide and Pop + + + + 6 + F1 + + FDIVRP + ST1 + ST + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide and Pop + + + + 7 + + FIDIVRSTMwi + + x87fpuarith + 0123 + 1 + 023 + Reverse Divide + + + 7 + + FDIVPESTST + + x87fpuarith + 0123 + 1 + 023 + Divide and Pop + + + + 7 + F9 + + FDIVP + ST1 + ST + + x87fpuarith + 0123 + 1 + 023 + Divide and Pop + + + + + + + + 0 + + FILDSTMwi + + x87fpudatamov + 0123 + 1 + 023 + Load Integer + + + 0 + + FFREEPEST + + x87fpucontrol + 0123 + 0123 + Free Floating-Point Register and Pop + + + + 1 + 10 + + FISTTPMwiST + + sse3 + x87fpu + + conver + 0123 + 1 + 023 + b + Store Integer with Truncation and Pop + + + 1 + 02 + + FXCH7STEST + + x87fpudatamov + 0123 + 1 + 023 + Exchange Register Contents + + + 1 + 03 + + FXCH7STEST + + x87fpudatamov + 0123 + 1 + 023 + Exchange Register Contents + + + + 2 + + FISTMwiST + + x87fpudatamov + 0123 + 1 + 023 + Store Integer + + + 2 + 02 + + + FSTP8ESTST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + 2 + 03 + + + FSTP8ESTST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + + 3 + + FISTPMwiST + + x87fpudatamov + 0123 + 1 + 023 + Store Integer and Pop + + + 3 + 02 + + + FSTP9ESTST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + 3 + 03 + + + FSTP9ESTST + + x87fpudatamov + 0123 + 1 + 023 + Store Floating Point Value and Pop + + + + + 4 + + FBLDSTMbcd + + x87fpudatamov + 0123 + 1 + 023 + Load Binary Coded Decimal + + + + 4 + E0 + 02 + + FNSTSWAX + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Status Word + + + + 4 + 9B + E0 + 02 + + FSTSWAX + + x87fpucontrol + 0123 + 0123 + Store x87 FPU Status Word + + + + 5 + + FILDSTMqi + + x87fpudatamov + 0123 + 1 + 023 + Load Integer + + + 5 + 07 + + FUCOMIPSTEST + + x87fpucompar + ozpc + ozpc + o + 1 + 1 + Unordered Compare Floating Point Values and Set EFLAGS and Pop + + + + 6 + + FBSTPMbcdST + + x87fpudatamov + 0123 + 1 + 023 + Store BCD Integer and Pop + + + 6 + 07 + + FCOMIPSTEST + + x87fpucompar + ozpc + ozpc + o + 1 + 1 + Compare Floating Point Values and Set EFLAGS and Pop + + + + + 7 + + FISTPMqiST + + x87fpudatamov + 0123 + 1 + 023 + Store Integer and Pop + + + + + + + + + LOOPNZ + + eCX + Jbs + + + LOOPNE + + eCX + Jbs + + genbranchcond + z + Decrement count; Jump short if count!=0 and ZF=0 + + + + 10 + + LOOPNZ + rCX + Jbs + + + LOOPNE + rCX + Jbs + + genbranchcond + z + Decrement count; Jump short if count!=0 and ZF=0 + + + + + + + LOOPZ + + eCX + Jbs + + + LOOPE + + eCX + Jbs + + genbranchcond + z + Decrement count; Jump short if count!=0 and ZF=1 + + + + 10 + + LOOPZ + rCX + Jbs + + + LOOPE + rCX + Jbs + + genbranchcond + z + Decrement count; Jump short if count!=0 and ZF=1 + + + + + + + LOOP + + eCX + Jbs + + genbranchcond + Decrement count; Jump short if count!=0 + + + + 10 + + LOOP + rCX + Jbs + + genbranchcond + Decrement count; Jump short if count!=0 + + + + + + + JCXZ + Jbs + CX + + + JECXZ + Jbs + ECX + + genbranchcond + Jump short if eCX register is 0 + + + 10 + + JECXZ + Jbs + ECX + + + JRCXZ + Jbs + RCX + + genbranchcond + Jump short if rCX register is 0 + + + + + + + IN + AL + Ib + + geninout + Input from Port + + + + + + + IN + eAX + Ib + + geninout + Input from Port + + + + + + + OUT + Ib + AL + + geninout + Output to Port + + + + + + + OUT + Ib + eAX + + geninout + Output to Port + + + + + + + + + CALL + SS:[rSP] + Jvds + + genbranchstack + Call Procedure + + + + + + + + JMPJvds + genbranch + Jump + + + + + + JMPFAp + genbranch + Jump + + + 10 + + Invalid Instruction in 64-Bit Mode + + + + + + JMPJbs + genbranch + Jump + + + + + + + IN + AL + DX + + geninout + Input from Port + + + + + + + IN + eAX + DX + + geninout + Input from Port + + + + + + + OUT + DX + AL + + geninout + Output to Port + + + + + + + OUT + DX + eAX + + geninout + Output to Port + + + + + + LOCK + prefix + Assert LOCK# Signal Prefix + + + + + + + Undefined and Reserved; Does not Generate #UD + + + 03 + + INT1 + SS:[rSP] + eFlags + + + ICEBP + SS:[rSP] + eFlags + + genbreakstack + + iii + Call to Interrupt Procedure + + + + + + + REPNZ + eCX + + + REPNE + eCX + + prefixstring + z + Repeat String Operation Prefix + + + + REP + eCX + + prefixstring + Repeat String Operation Prefix + + + + 10 + + REPNZ + rCX + + + REPNE + rCX + + prefixstring + z + Repeat String Operation Prefix + + + 10 + + REP + rCX + + prefixstring + Repeat String Operation Prefix + + + + 10 + + sse2 + prefix + Scalar Double-precision Prefix + + + + + + + REPZ + eCX + + + REPE + eCX + + prefixstring + z + Repeat String Operation Prefix + + + + REP + rCX + + prefixstring + Repeat String Operation Prefix + + + + 10 + + REPZ + rCX + + + REPE + rCX + + prefixstring + z + Repeat String Operation Prefix + + + 10 + + REP + rCX + + prefixstring + Repeat String Operation Prefix + + + + 09 + + sse1 + prefix + Scalar Single-precision Prefix + + + + + + HLT + system + Halt + + + + + + CMC + genflgctrl + ccc + Complement Carry Flag + + + + + + 0 + TESTEbIb + genlogical + oszapcoszpcaoc + Logical Compare + + + 1 + TESTEbIb + genlogical + oszapcoszpcaoc + Logical Compare + + + 2 + NOTEb + genlogical + One's Complement Negation + + + 3 + NEGEb + genarithbinary + oszapcoszapc + Two's Complement Negation + + + 4 + + MUL + AX + AL + Eb + + genarithbinary + oszapcocszap + Unsigned Multiply + + + 5 + + IMUL + AX + AL + Eb + + genarithbinary + oszapcocszap + Signed Multiply + + + 6 + + DIV + AL + AH + AX + Eb + + genarithbinary + oszapcoszapc + Unsigned Divide + + + 7 + + IDIV + AL + AH + AX + Eb + + genarithbinary + oszapcoszapc + Signed Divide + + + + + + 0 + TESTEvqpIvqp + genlogical + oszapcoszpcaoc + Logical Compare + + + 1 + TESTEvqpIvqp + genlogical + oszapcoszpcaoc + Logical Compare + + + 2 + NOTEvqp + genlogical + One's Complement Negation + + + 3 + NEGEvqp + genarithbinary + oszapcoszapc + Two's Complement Negation + + + 4 + + MUL + rDX + rAX + Evqp + + genarithbinary + oszapcocszap + Unsigned Multiply + + + 5 + + IMUL + rDX + rAX + Evqp + + genarithbinary + oszapcocszap + Signed Multiply + + + 6 + + DIV + rDX + rAX + Evqp + + genarithbinary + oszapcoszapc + Unsigned Divide + + + 7 + + IDIV + rDX + rAX + Evqp + + genarithbinary + oszapcoszapc + Signed Divide + + + + + + CLC + genflgctrl + ccc + Clear Carry Flag + + + + + + STC + genflgctrl + ccC + Set Carry Flag + + + + + + CLI + genflgctrl + iii + Clear Interrupt Flag + + + + + + STI + genflgctrl + iiI + Set Interrupt Flag + + + + + + CLD + genflgctrl + ddd + Clear Direction Flag + + + + + + STD + genflgctrl + ddD + Set Direction Flag + + + + + + 0 + INCEb + genarithbinary + oszaposzap + Increment by 1 + + + 1 + DECEb + genarithbinary + oszaposzap + Decrement by 1 + + + + + + 0 + INCEvqp + genarithbinary + oszaposzap + Increment by 1 + + + 1 + DECEvqp + genarithbinary + oszaposzap + Decrement by 1 + + + 2 + + CALL + SS:[rSP] + Ev + + genbranchstack + Call Procedure + + + 2 + 10 + + CALL + SS:[rSP] + Eq + + genbranchstack + Call Procedure + + + 3 + + CALLF + SS:[rSP] + Mptp + + genbranchstack + Call Procedure + + + 4 + JMPEv + genbranch + Jump + + + 4 + 10 + JMPEq + genbranch + Jump + + + 5 + JMPFMptp + genbranch + Jump + + + 6 + + PUSH + SS:[rSP] + Ev + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + 6 + 10 + + PUSH + SS:[rSP] + Evq + + genstack + Push Word, Doubleword or Quadword Onto the Stack + + + + + + + + + 02 + + 0 + + SLDT + Mw + LDTR + + + SLDT + Rvqp + LDTR + + system + Store Local Descriptor Table Register + + + 1 + + STR + Mw + TR + + + STR + Rvqp + TR + + system + Store Task Register + + + 2 + + LLDT + LDTR + Ew + + system + Load Local Descriptor Table Register + + + 3 + + LTR + TR + Ew + + system + Load Task Register + + + 4 + VERREw + system + zz + Verify a Segment for Reading + + + 5 + VERWEw + system + zz + Verify a Segment for Writing + + + 6 + 99 + JMPE + systembranch + Jump to IA-64 Instruction Set + + + + + 02 + + 0 + + SGDT + Ms + GDTR + + system + Store Global Descriptor Table Register + + + + 0 + C1 + 10 + + VMCALL + + vmx + + oszapc + oszapc + + Call to VM Monitor + Call to VM monitor by causing VM exit + + + + + 0 + C2 + 10 + + VMLAUNCH + + vmx + + oszapc + oszapc + + Launch Virtual Machine + Launch virtual machine managed by current VMCS + + + + + 0 + C3 + 10 + + VMRESUME + + vmx + + oszapc + oszapc + + Resume Virtual Machine + Resume virtual machine managed by current VMCS + + + + + 0 + C4 + 10 + + VMXOFF + + vmx + + oszapc + oszapc + + Leave VMX Operation + Leaves VMX operation + + + + + 1 + + SIDT + Ms + IDTR + + system + Store Interrupt Descriptor Table Register + + + + 1 + C8 + 10 + + MONITOR + (DS:)[rAX] + ECX + EDX + + sse3 + sync + Set Up Monitor Address + + + 1 + C9 + 10 + + MWAIT + EAX + ECX + + sse3 + sync + Monitor Wait + + + + 2 + + LGDT + GDTR + Ms + + system + Load Global Descriptor Table Register + + + 2 + D0 + 12 + + XGETBV + EDX + EAX + ECX + XCR + + system + + Get Value of Extended Control Register + Reads an XCR specified by ECX into EDX:EAX + + + + 2 + D1 + 12 + + XSETBV + XCR + ECX + EDX + EAX + + system + + Set Extended Control Register + Write the value in EDX:EAX to the XCR specified by ECX + + + + + 3 + + LIDT + IDTR + Ms + + system + Load Interrupt Descriptor Table Register + + + + 4 + + SMSW + Mw + MSW + + + SMSW + Rvqp + MSW + + system + Store Machine Status Word + + + + + 6 + + LMSW + MSW + Ew + + system + Load Machine Status Word + + + + + + 7 + 04 + + INVLPG + M + + system + Invalidate TLB Entry + + + 7 + F8 + 10 + + SWAPGS + GS + IA32_KERNEL_GSBASE + + system + Swap GS Base Register + + + + 7 + F9 + 13 + + RDTSCP + EAX + EDX + ECX + IA32_TIME_STAMP_COUNTER + IA32_TSC_AUX + + system + + Read Time-Stamp Counter and Processor ID + Read 64-bit time-stamp counter and 32-bit IA32_TSC_AUX value into EDX:EAX and ECX + + + + + + + + 02 + LARGvqpMw + LARGvqpRv + system + zz + Load Access Rights Byte + + + + + + 02 + LSLGvqpMw + LSLGvqpRv + system + zz + Load Segment Limit + + + + + + + + 02 + 02 + + LOADALL + AX + CX + DX + BX + SP + BP + SI + DI + Flags + ES + SS + DS + MSW + TR + LDTR + GDTR + IDTR + + systembranch + + Load All of the CPU Registers + + + 10 + + SYSCALL + RCX + R11 + SS + + EFlags + IA32_LSTAR + IA32_FMASK + + systembranch + Fast System Call + + + + + + + 02 + + CLTS + CR0 + + system + Clear Task-Switched Flag in CR0 + + + + + + 03 + 03 + + LOADALL + EAX + ECX + EDX + EBX + ESP + EBP + ESI + EDI + EFlags + ES + SS + DS + FS + GS + CR0 + DR6 + DR7 + TR + LDTR + GDTR + IDTR + + systembranch + + Load All of the CPU Registers + + + 10 + + SYSRET + SS + EFlags + R11 + RCX + IA32_STAR + + systembranchtrans + + Return From Fast System Call + + + + + + 04 + INVD + system + Invalidate Internal Caches + + + + + + 04 + WBINVD + system + Write Back and Invalidate Cache + + + + + + + + 02 + UD2 + gencontrol + Undefined Instruction + + + + + + + + 07 + NOPEv + gencontrol + No Operation + + + + + + + + + + 09 + + MOVUPS + Vps + Wps + + sse1 + simdfp + datamov + Move Unaligned Packed Single-FP Values + + + + F3 + 09 + + MOVSS + Vss + Wss + + sse1 + simdfp + datamov + Move Scalar Single-FP Values + + + + 66 + 10 + + MOVUPD + Vpd + Wpd + + sse2 + pcksclr + datamov + Move Unaligned Packed Double-FP Value + + + + F2 + 10 + + MOVSD + Vsd + Wsd + + sse2 + pcksclr + datamov + Move Scalar Double-FP Value + + + + + + 09 + + MOVUPS + Wps + Vps + + sse1 + simdfp + datamov + Move Unaligned Packed Single-FP Values + + + + F3 + 09 + + MOVSS + Wss + Vss + + sse1 + simdfp + datamov + Move Scalar Single-FP Values + + + + 66 + 10 + + MOVUPD + Wpd + Vpd + + sse2 + pcksclr + datamov + Move Unaligned Packed Double-FP Values + + + + F2 + 10 + + MOVSD + Wsd + Vsd + + sse2 + pcksclr + datamov + Move Scalar Double-FP Value + + + + + + + + 09 + + MOVHLPS + Vq + Uq + + sse1 + simdfp + datamov + Move Packed Single-FP Values High to Low + + + + 09 + + MOVLPS + Vq + Mq + + sse1 + simdfp + datamov + Move Low Packed Single-FP Values + + + + 66 + 10 + + MOVLPD + Vq + Mq + + sse2 + pcksclr + datamov + Move Low Packed Double-FP Value + + + + F2 + 10 + + MOVDDUP + Vq + Wq + + sse3 + simdfp + datamov + Move One Double-FP and Duplicate + + + + F3 + 10 + + MOVSLDUP + Vq + Wq + + sse3 + simdfp + datamov + Move Packed Single-FP Low and Duplicate + + + + + + 09 + + MOVLPS + Mq + Vq + + sse1 + simdfp + datamov + Move Low Packed Single-FP Values + + + + 66 + 10 + + MOVLPD + Mq + Vq + + sse2 + pcksclr + datamov + Move Low Packed Double-FP Value + + + + + + 09 + + UNPCKLPS + Vps + Wq + + sse1 + simdfp + shunpck + Unpack and Interleave Low Packed Single-FP Values + + + + 66 + 10 + + UNPCKLPD + Vpd + Wpd + + sse2 + pcksclr + shunpck + Unpack and Interleave Low Packed Double-FP Values + + + + + + 09 + + UNPCKHPS + Vps + Wq + + sse1 + simdfp + shunpck + Unpack and Interleave High Packed Single-FP Values + + + + 66 + 10 + + UNPCKHPD + Vpd + Wpd + + sse2 + pcksclr + shunpck + Unpack and Interleave High Packed Double-FP Values + + + + + + 09 + + MOVLHPS + Vq + Uq + + sse1 + simdfp + datamov + Move Packed Single-FP Values Low to High + + + + 09 + + MOVHPS + Vq + Mq + + sse1 + simdfp + datamov + Move High Packed Single-FP Values + + + + 66 + 10 + + MOVHPD + Vq + Mq + + sse2 + pcksclr + datamov + Move High Packed Double-FP Value + + + + F3 + 10 + + MOVSHDUP + Vq + Wq + + sse3 + simdfp + datamov + Move Packed Single-FP High and Duplicate + + + + + + 09 + + MOVHPS + Mq + Vq + + sse1 + simdfp + datamov + Move High Packed Single-FP Values + + + + 66 + 10 + + MOVHPD + Mq + Vq + + sse2 + pcksclr + datamov + Move High Packed Double-FP Value + + + + + + + + 07 + 08 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 0 + 09 + + PREFETCHNTA + Mb + + sse1 + fetch + Prefetch Data Into Caches + + + + 1 + 09 + + PREFETCHT0 + Mb + + sse1 + fetch + Prefetch Data Into Caches + + + + 2 + 09 + + PREFETCHT1 + Mb + + sse1 + fetch + Prefetch Data Into Caches + + + + 3 + 09 + + PREFETCHT2 + Mb + + sse1 + fetch + Prefetch Data Into Caches + + + + 4 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 5 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 6 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 7 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + + + 07 + 08 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 0 + 10 + + NOP + Ev + + gen + control + No Operation + + + + 1 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 2 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 3 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 4 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 5 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 6 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + 7 + 07 + + HINT_NOP + Ev + + gen + control + + Hintable NOP + + + + + + + + + + 03 + + MOV + Rd + Cd + + system + oszapcoszapc + Move to/from Control Registers + + + + 03 + + MOV + Hd + Cd + + system + oszapcoszapc + Move to/from Control Registers + + + + 10 + + MOV + Rq + Cq + + system + oszapcoszapc + Move to/from Control Registers + + + + 10 + + MOV + Hq + Cq + + system + oszapcoszapc + Move to/from Control Registers + + + + + + + + 03 + + MOV + + + Rd + Dd + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + + + Hd + Dd + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Rq + Dq + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Hq + Dq + + system + oszapcoszapc + Move to/from Debug Registers + + + + + + + + 03 + + MOV + Cd + Rd + + system + oszapcoszapc + Move to/from Control Registers + + + 03 + + MOV + Cd + Hd + + system + oszapcoszapc + Move to/from Control Registers + + + 10 + + MOV + Cq + Rq + + system + oszapcoszapc + Move to/from Control Registers + + + 10 + + MOV + Cq + Hq + + system + oszapcoszapc + Move to/from Control Registers + + + + + + + + 03 + + MOV + + + Dd + Rd + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + + + Dq + Hq + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Dq + Rq + + system + oszapcoszapc + Move to/from Debug Registers + + + + 03 + + MOV + Dq + Hq + + system + oszapcoszapc + Move to/from Debug Registers + + + + + + + + 03 + 04 + + MOV + Rd + Td + + system + oszapcoszapc + Move to/from Test Registers + + + 03 + 04 + + MOV + Hd + Td + + system + oszapcoszapc + Move to/from Test Registers + + + + + + + + + + 03 + 04 + + MOV + Td + Rd + + system + oszapcoszapc + Move to/from Test Registers + + + 03 + 04 + + MOV + Td + Hd + + system + oszapcoszapc + Move to/from Test Registers + + + + + + + + 09 + + MOVAPS + Vps + Wps + + sse1 + simdfp + datamov + Move Aligned Packed Single-FP Values + + + + 66 + 10 + + MOVAPD + Vpd + Wpd + + sse2 + pcksclr + datamov + Move Aligned Packed Double-FP Values + + + + + + 09 + + MOVAPS + Wps + Vps + + sse1 + simdfp + datamov + Move Aligned Packed Single-FP Values + + + + 66 + 10 + + MOVAPD + Wpd + Vpd + + sse2 + pcksclr + datamov + Move Aligned Packed Double-FP Values + + + + + + 09 + + CVTPI2PS + Vps + Qpi + + sse1 + conver + Convert Packed DW Integers to Single-FP Values + + + + F3 + 09 + + CVTSI2SS + Vss + Edqp + + sse1 + conver + Convert DW Integer to Scalar Single-FP Value + + + + 66 + 10 + + CVTPI2PD + Vpd + Qpi + + sse2 + pcksclr + conver + Convert Packed DW Integers to Double-FP Values + + + + F2 + 10 + + CVTSI2SD + Vsd + Edqp + + sse2 + pcksclr + conver + Convert DW Integer to Scalar Double-FP Value + + + + + + 09 + + MOVNTPS + Mps + Vps + + sse1 + cachect + Store Packed Single-FP Values Using Non-Temporal Hint + + + + 66 + 10 + + MOVNTPD + Mpd + Vpd + + sse2 + cachect + Store Packed Double-FP Values Using Non-Temporal Hint + + + + + + 09 + + CVTTPS2PI + Ppi + Wpsq + + sse1 + conver + Convert with Trunc. Packed Single-FP Values to DW Integers + + + + F3 + 09 + + CVTTSS2SI + Gdqp + Wss + + sse1 + conver + Convert with Trunc. Scalar Single-FP Value to DW Integer + + + + 66 + 10 + + CVTTPD2PI + Ppi + Wpd + + sse2 + pcksclr + conver + Convert with Trunc. Packed Double-FP Values to DW Integers + + + + F2 + 10 + + CVTTSD2SI + Gdqp + Wsd + + sse2 + pcksclr + conver + Conv. with Trunc. Scalar Double-FP Value to Signed DW Int + + + + + + 09 + + CVTPS2PI + Ppi + Wpsq + + sse1 + conver + Convert Packed Single-FP Values to DW Integers + + + + F3 + 09 + + CVTSS2SI + Gdqp + Wss + + sse1 + conver + Convert Scalar Single-FP Value to DW Integer + + + + 66 + 10 + + CVTPD2PI + Ppi + Wpd + + sse2 + pcksclr + conver + Convert Packed Double-FP Values to DW Integers + + + + F2 + 10 + + CVTSD2SI + Gdqp + Wsd + + sse2 + pcksclr + conver + Convert Scalar Double-FP Value to DW Integer + + + + + + 09 + + UCOMISS + Vss + Wss + + sse1 + simdfp + compar + zpczpc + Unordered Compare Scalar Single-FP Values and Set EFLAGS + + + + 66 + 10 + + UCOMISD + Vsd + Wsd + + sse2 + pcksclr + compar + zpczpc + Unordered Compare Scalar Double-FP Values and Set EFLAGS + + + + + + 09 + + COMISS + Vss + Wss + + sse1 + simdfp + compar + zpczpc + Compare Scalar Ordered Single-FP Values and Set EFLAGS + + + + 66 + 10 + + COMISD + Vsd + Wsd + + sse2 + pcksclr + compar + zpczpc + Compare Scalar Ordered Double-FP Values and Set EFLAGS + + + + + + 05 + + WRMSR + MSR + rCX + rAX + rDX + + system + Write to Model Specific Register + + + + + + 05 + + RDTSC + EAX + EDX + IA32_TIME_STAMP_COUNTER + + system + Read Time-Stamp Counter + + + + + + 05 + + RDMSR + rAX + rDX + rCX + MSR + + system + Read from Model Specific Register + + + + + + 06 + + RDPMC + EAX + EDX + PMC + + system + Read Performance-Monitoring Counters + + + + + + + + + 08 + + SYSENTER + SS + ESP + IA32_SYSENTER_CS + IA32_SYSENTER_ESP + IA32_SYSENTER_EIP + + system + branch + iii + Fast System Call + + + 10 + + SYSENTER + SS + RSP + IA32_SYSENTER_CS + IA32_SYSENTER_ESP + IA32_SYSENTER_EIP + + system + branch + iii + Fast System Call + + + + + + + + 08 + + SYSEXIT + SS + eSP + IA32_SYSENTER_CS + rCX + rDX + + system + branch + trans + Fast Return from Fast System Call + + + + + + + + 12 + + GETSEC + EAX + + smx + + GETSEC Leaf Functions + + + + + + + + + + + + 00 + 12 + + PSHUFB + Pq + Qq + + ssse3 + simdint + Packed Shuffle Bytes + + + 66 + 00 + 12 + + PSHUFB + Vdq + Wdq + + ssse3 + simdint + Packed Shuffle Bytes + + + + + + 01 + 12 + + PHADDW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Add + + + 66 + 01 + 12 + + PHADDW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Add + + + + + + 02 + 12 + + PHADDD + Pq + Qq + + ssse3 + simdint + Packed Horizontal Add + + + 66 + 02 + 12 + + PHADDD + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Add + + + + + + 03 + 12 + + PHADDSW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Add and Saturate + + + 66 + 03 + 12 + + PHADDSW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Add and Saturate + + + + + + 04 + 12 + + PMADDUBSW + Pq + Qq + + ssse3 + simdint + Multiply and Add Packed Signed and Unsigned Bytes + + + 66 + 04 + 12 + + PMADDUBSW + Vdq + Wdq + + ssse3 + simdint + Multiply and Add Packed Signed and Unsigned Bytes + + + + + + 05 + 12 + + PHSUBW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Subtract + + + 66 + 05 + 12 + + PHSUBW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Subtract + + + + + + 06 + 12 + + PHSUBD + Pq + Qq + + ssse3 + simdint + Packed Horizontal Subtract + + + 66 + 06 + 12 + + PHSUBD + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Subtract + + + + + + 07 + 12 + + PHSUBSW + Pq + Qq + + ssse3 + simdint + Packed Horizontal Subtract and Saturate + + + 66 + 07 + 12 + + PHSUBSW + Vdq + Wdq + + ssse3 + simdint + Packed Horizontal Subtract and Saturate + + + + + + 08 + 12 + + PSIGNB + Pq + Qq + + ssse3 + simdint + Packed SIGN + + + 66 + 08 + 12 + + PSIGNB + Vdq + Wdq + + ssse3 + simdint + Packed SIGN + + + + + + 09 + 12 + + PSIGNW + Pq + Qq + + ssse3 + simdint + Packed SIGN + + + 66 + 09 + 12 + + PSIGNW + Vdq + Wdq + + ssse3 + simdint + Packed SIGN + + + + + + 0A + 12 + + PSIGND + Pq + Qq + + ssse3 + simdint + Packed SIGN + + + 66 + 0A + 12 + + PSIGND + Vdq + Wdq + + ssse3 + simdint + Packed SIGN + + + + + + 0B + 12 + + PMULHRSW + Pq + Qq + + ssse3 + simdint + Packed Multiply High with Round and Scale + + + 66 + 0B + 12 + + PMULHRSW + Vdq + Wdq + + ssse3 + simdint + Packed Multiply High with Round and Scale + + + + + + 66 + 10 + 12 + + PBLENDVB + Vdq + Wdq + XMM0 + + sse41 + simdint + datamov + + Variable Blend Packed Bytes + + + + + + + 66 + 14 + 12 + + BLENDVPS + Vps + Wps + XMM0 + + sse41 + simdint + datamov + + Variable Blend Packed Single-FP Values + + + + + + + 66 + 15 + 12 + + BLENDVPD + Vpd + Wpd + XMM0 + + sse41 + simdint + datamov + + Variable Blend Packed Double-FP Values + + + + + + + 66 + 17 + 12 + + PTEST + Vdq + Wdq + + sse41 + oszapc + oszapc + osap + + Logical Compare + + + + + + + 1C + 12 + + PABSB + Pq + Qq + + ssse3 + simdint + Packed Absolute Value + + + 66 + 1C + 12 + + PABSB + Vdq + Wdq + + ssse3 + simdint + Packed Absolute Value + + + + + + 1D + 12 + + PABSW + Pq + Qq + + ssse3 + simdint + Packed Absolute Value + + + 66 + 1D + 12 + + PABSW + Vdq + Wdq + + ssse3 + simdint + Packed Absolute Value + + + + + + 1E + 12 + + PABSD + Pq + Qq + + ssse3 + simdint + Packed Absolute Value + + + 66 + 1E + 12 + + PABSD + Vdq + Wdq + + ssse3 + simdint + Packed Absolute Value + + + + + + 66 + 20 + 12 + + PMOVSXBW + Vdq + Mq + + + PMOVSXBW + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 21 + 12 + + PMOVSXBD + Vdq + Md + + + PMOVSXBD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 22 + 12 + + PMOVSXBQ + Vdq + Mw + + + PMOVSXBQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 23 + 12 + + PMOVSXWD + Vdq + Mq + + + PMOVSXWD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 24 + 12 + + PMOVSXWQ + Vdq + Md + + + PMOVSXWQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 25 + 12 + + PMOVSXDQ + Vdq + Mq + + + PMOVSXDQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Sign Extend + + + + + + + 66 + 28 + 12 + + PMULDQ + Vdq + Wdq + + sse41 + simdint + arith + + Multiply Packed Signed Dword Integers + + + + + + + 66 + 29 + 12 + + PCMPEQQ + Vdq + Wdq + + sse41 + simdint + compar + + Compare Packed Qword Data for Equal + + + + + + + 66 + 2A + 12 + + MOVNTDQA + Vdq + Mdq + + sse41 + cachect + + Load Double Quadword Non-Temporal Aligned Hint + + + + + + + 66 + 2B + 12 + + PACKUSDW + Vdq + Wdq + + sse41 + simdint + conver + + Pack with Unsigned Saturation + + + + + + + 66 + 30 + 12 + + PMOVZXBW + Vdq + Mq + + + PMOVZXBW + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 31 + 12 + + PMOVZXBD + Vdq + Md + + + PMOVZXBD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 32 + 12 + + PMOVZXBQ + Vdq + Mw + + + PMOVZXBQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 33 + 12 + + PMOVZXWD + Vdq + Mq + + + PMOVZXWD + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 34 + 12 + + PMOVZXWQ + Vdq + Md + + + PMOVZXWQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 35 + 12 + + PMOVZXDQ + Vdq + Mq + + + PMOVZXDQ + Vdq + Udq + + sse41 + simdint + conver + + Packed Move with Zero Extend + + + + + + + 66 + 37 + 12 + + PCMPGTQ + Vdq + Wdq + + sse42 + simdint + compar + + Compare Packed Qword Data for Greater Than + Compare packed qwords in xmm2/m128 and xmm1 for greater than + + + + + + + 66 + 38 + 12 + + PMINSB + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Signed Byte Integers + + + + + + + 66 + 39 + 12 + + PMINSD + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Signed Dword Integers + + + + + + + 66 + 3A + 12 + + PMINUW + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Unsigned Word Integers + + + + + + + 66 + 3B + 12 + + PMINUD + Vdq + Wdq + + sse41 + simdint + compar + + Minimum of Packed Unsigned Dword Integers + + + + + + + 66 + 3C + 12 + + PMAXSB + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Signed Byte Integers + + + + + + + 66 + 3D + 12 + + PMAXSD + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Signed Dword Integers + + + + + + + 66 + 3E + 12 + + PMAXUW + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Unsigned Word Integers + + + + + + + 66 + 3F + 12 + + PMAXUD + Vdq + Wdq + + sse41 + simdint + compar + + Maximum of Packed Unsigned Dword Integers + + + + + + + 66 + 40 + 12 + + PMULLD + Vdq + Wdq + + sse41 + simdint + arith + + Multiply Packed Signed Dword Integers and Store Low Result + + + + + + + 66 + 41 + 12 + + PHMINPOSUW + Vdq + Wdq + + sse41 + simdint + compar + + Packed Horizontal Word Minimum + + + + + + + 66 + 80 + 12 + + INVEPT + Gd + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Derived from EPT + Invalidates EPT-derived entries in the TLBs and paging-structure caches + + + + + 66 + 80 + 12 + + INVEPT + Gq + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Derived from EPT + Invalidates EPT-derived entries in the TLBs and paging-structure caches + + + + + + + 66 + 81 + 12 + + INVVPID + Gd + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Based on VPID + Invalidates entries in the TLBs and paging-structure caches based on VPID + + + + + 66 + 81 + 12 + + INVVPID + Gq + Mdq + + vmx + + oszapc + oszapc + + Invalidate Translations Based on VPID + Invalidates entries in the TLBs and paging-structure caches based on VPID + + + + + + + F0 + 12 + + MOVBE + Gvqp + Mvqp + + gen + datamov + + Move Data After Swapping Bytes + Reverse byte order in op2 and move to op1 + + + + + F2 + F0 + 12 + + CRC32 + Gdqp + Eb + + sse42 + + Accumulate CRC32 Value + Accumulate CRC32 on r/m8 + + + + + + + F1 + 12 + + MOVBE + Mvqp + Gvqp + + gen + datamov + + Move Data After Swapping Bytes + Reverse byte order in op2 and move to op1 + + + + + F2 + F1 + 12 + + CRC32 + Gdqp + Evqp + + sse42 + + Accumulate CRC32 Value + Accumulate CRC32 on r/m8 + + + + + + + + + + + + 66 + 08 + 12 + + ROUNDPS + Vps + Wps + Ib + + sse41 + simdfp + conver + Round Packed Single-FP Values + + + + + + 66 + 09 + 12 + + ROUNDPD + Vps + Wpd + Ib + + sse41 + simdfp + conver + Round Packed Double-FP Values + + + + + + 66 + 0A + 12 + + ROUNDSS + Vss + Wss + Ib + + sse41 + simdfp + conver + Round Scalar Single-FP Values + + + + + + 66 + 0B + 12 + + ROUNDSD + Vsd + Wsd + Ib + + sse41 + simdfp + conver + Round Scalar Double-FP Values + + + + + + 66 + 0C + 12 + + BLENDPS + Vps + Wps + Ib + + sse41 + simdfp + datamov + + Blend Packed Single-FP Values + + + + + + + 66 + 0D + 12 + + BLENDPD + Vpd + Wpd + Ib + + sse41 + simdfp + datamov + + Blend Packed Double-FP Values + + + + + + + 66 + 0E + 12 + + PBLENDW + Vdq + Wdq + Ib + + sse41 + simdint + datamov + + Blend Packed Words + + + + + + + 0F + 12 + + PALIGNR + Pq + Qq + + ssse3 + simdint + Packed Align Right + + + 66 + 0F + 12 + + PALIGNR + Vdq + Wdq + + ssse3 + simdint + Packed Align Right + + + + + + 66 + 14 + 12 + + PEXTRB + Mb + Vdq + Ib + + + PEXTRB + Rdqp + Vdq + Ib + + sse41 + simdint + datamov + + Extract Byte + + + + + + + 66 + 15 + 12 + + PEXTRW + Mw + Vdq + Ib + + + PEXTRW + Rdqp + Vdq + Ib + + sse41 + simdint + datamov + + Extract Word + + + + + + + 66 + 16 + 12 + + PEXTRD + Ed + Vdq + Ib + + + PEXTRQ + Eqp + Vdq + Ib + + sse41 + simdint + datamov + + Extract Dword/Qword + + + + + + + 66 + 17 + 12 + + + EXTRACTPS + Ed + Vdq + Ib + + sse41 + simdfp + datamov + + Extract Packed Single-FP Value + + + + + + + 66 + 20 + 12 + + PINSRB + Vdq + Mb + Ib + + + + PINSRB + Vdq + Rdqp + Ib + + sse41 + simdint + datamov + Insert Byte + + + + + + 66 + 21 + 12 + + INSERTPS + Vps + Ups + Ib + + + INSERTPS + Vps + Md + Ib + + sse41 + simdfp + datamov + + Insert Packed Single-FP Value + + + + + + + 66 + 22 + 12 + + PINSRD + Vdq + Ed + Ib + + + PINSRQ + Vdq + Eqp + Ib + + sse41 + simdint + datamov + Insert Dword/Qword + + + + + + 66 + 40 + 12 + + DPPS + Vps + Wps + + sse41 + simdfp + arith + + Dot Product of Packed Single-FP Values + + + + + + + 66 + 41 + 12 + + DPPD + Vpd + Wpd + + sse41 + simdfp + arith + + Dot Product of Packed Double-FP Values + + + + + + + 66 + 42 + 12 + + MPSADBW + Vdq + Wdq + Ib + + sse41 + simdint + arith + + Compute Multiple Packed Sums of Absolute Difference + + + + + + + 66 + 60 + 12 + + PCMPESTRM + XMM0 + Vdq + Wdq + Ib + rAX + rDX + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Explicit Length Strings, Return Mask + Perform a packed comparison of string data with + explicit lengths, generating a mask, and storing the result + in XMM0 + + + + + + + 66 + 61 + 12 + + PCMPESTRI + rCX + Vdq + Wdq + Ib + rAX + rDX + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Explicit Length Strings, Return Index + Perform a packed comparison of string data with + explicit lengths, generating an index, and storing the + result in rCX + + + + + + + 66 + 62 + 12 + + PCMPISTRM + XMM0 + Vdq + Wdq + Ib + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Implicit Length Strings, Return Mask + Perform a packed comparison of string data with + implicit lengths, generating a mask, and storing the result + in XMM0 + + + + + + + 66 + 63 + 12 + + PCMPISTRI + rCX + Vdq + Wdq + Ib + + sse42 + strtxt + oszapc + oszapc + ap + + Packed Compare Implicit Length Strings, Return Index + Perform a packed comparison of string data with + implicit lengths, generating an index, and storing the + result in rCX + + + + + + + + + + 07 + CMOVOGvqpEvqp + gendatamov + o + Conditional Move - overflow (OF=1) + + + + + + 07 + CMOVNOGvqpEvqp + gendatamov + o + Conditional Move - not overflow (OF=0) + + + + + + 07 + CMOVBGvqpEvqp + CMOVNAEGvqpEvqp + CMOVCGvqpEvqp + gendatamov + c + Conditional Move - below/not above or equal/carry (CF=1) + + + + + + 07 + CMOVNBGvqpEvqp + CMOVAEGvqpEvqp + CMOVNCGvqpEvqp + gendatamov + c + Conditional Move - not below/above or equal/not carry (CF=0) + + + + + + 07 + CMOVZGvqpEvqp + CMOVEGvqpEvqp + gendatamov + z + Conditional Move - zero/equal (ZF=0) + + + + + + 07 + CMOVNZGvqpEvqp + CMOVNEGvqpEvqp + gendatamov + z + Conditional Move - not zero/not equal (ZF=1) + + + + + + 07 + CMOVBEGvqpEvqp + CMOVNAGvqpEvqp + gendatamov + + zc + Conditional Move - below or equal/not above (CF=1 AND ZF=1) + + + + + + 07 + CMOVNBEGvqpEvqp + CMOVAGvqpEvqp + gendatamov + + zc + Conditional Move - not below or equal/above (CF=0 AND ZF=0) + + + + + + 07 + CMOVSGvqpEvqp + gendatamov + s + Conditional Move - sign (SF=1) + + + + + + 07 + CMOVNSGvqpEvqp + gendatamov + s + Conditional Move - not sign (SF=0) + + + + + + 07 + CMOVPGvqpEvqp + CMOVPEGvqpEvqp + gendatamov + p + Conditional Move - parity/parity even (PF=1) + + + + + + 07 + CMOVNPGvqpEvqp + CMOVPOGvqpEvqp + gendatamov + p + Conditional Move - not parity/parity odd + + + + + + 07 + CMOVLGvqpEvqp + CMOVNGEGvqpEvqp + gendatamov + os + Conditional Move - less/not greater (SF!=OF) + + + + + + 07 + CMOVNLGvqpEvqp + CMOVGEGvqpEvqp + gendatamov + os + Conditional Move - not less/greater or equal (SF=OF) + + + + + + 07 + CMOVLEGvqpEvqp + CMOVNGGvqpEvqp + gendatamov + osz + Conditional Move - less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + 07 + CMOVNLEGvqpEvqp + CMOVGGvqpEvqp + gendatamov + osz + Conditional Move - not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 09 + + MOVMSKPS + Gdqp + Ups + + sse1 + simdfp + datamov + Extract Packed Single-FP Sign Mask + + + + 66 + 10 + + MOVMSKPD + Gdqp + Upd + + sse2 + pcksclr + datamov + Extract Packed Double-FP Sign Mask + + + + + + 09 + + SQRTPS + Vps + Wps + + sse1 + simdfp + arith + Compute Square Roots of Packed Single-FP Values + + + + F3 + 09 + + SQRTSS + Vss + Wss + + sse1 + simdfp + arith + Compute Square Root of Scalar Single-FP Value + + + + 66 + 10 + + SQRTPD + Vpd + Wpd + + sse2 + pcksclr + arith + Compute Square Roots of Packed Double-FP Values + + + + F2 + 10 + + SQRTSD + Vsd + Wsd + + sse2 + pcksclr + arith + Compute Square Root of Scalar Double-FP Value + + + + + + 09 + + RSQRTPS + Vps + Wps + + sse1 + simdfp + arith + Compute Recipr. of Square Roots of Packed Single-FP Values + + + + F3 + 09 + + RSQRTSS + Vss + Wss + + sse1 + simdfp + arith + Compute Recipr. of Square Root of Scalar Single-FP Value + + + + + + 09 + + RCPPS + Vps + Wps + + sse1 + simdfp + arith + Compute Reciprocals of Packed Single-FP Values + + + + F3 + 09 + + RCPSS + Vss + Wss + + sse1 + simdfp + arith + Compute Reciprocal of Scalar Single-FP Values + + + + + + 09 + + ANDPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical AND of Packed Single-FP Values + + + + 66 + 10 + + ANDPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical AND of Packed Double-FP Values + + + + + + 09 + + ANDNPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical AND NOT of Packed Single-FP Values + + + + 66 + 10 + + ANDNPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical AND NOT of Packed Double-FP Values + + + + + + 09 + + ORPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical OR of Single-FP Values + + + + 66 + 10 + + ORPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical OR of Double-FP Values + + + + + + 09 + + XORPS + Vps + Wps + + sse1 + simdfp + logical + Bitwise Logical XOR for Single-FP Values + + + + 66 + 10 + + XORPD + Vpd + Wpd + + sse2 + pcksclr + logical + Bitwise Logical XOR for Double-FP Values + + + + + + 09 + + ADDPS + Vps + Wps + + sse1 + simdfp + arith + Add Packed Single-FP Values + + + + F3 + 09 + + ADDSS + Vss + Wss + + sse1 + simdfp + arith + Add Scalar Single-FP Values + + + + 66 + 10 + + ADDPD + Vpd + Wpd + + sse2 + pcksclr + arith + Add Packed Double-FP Values + + + + F2 + 10 + + ADDSD + Vsd + Wsd + + sse2 + pcksclr + arith + Add Scalar Double-FP Values + + + + + + 09 + + MULPS + Vps + Wps + + sse1 + simdfp + arith + Multiply Packed Single-FP Values + + + + F3 + 09 + + MULSS + Vss + Wss + + sse1 + simdfp + arith + Multiply Scalar Single-FP Value + + + + 66 + 10 + + MULPD + Vpd + Wpd + + sse2 + pcksclr + arith + Multiply Packed Double-FP Values + + + + F2 + 10 + + MULSD + Vsd + Wsd + + sse2 + pcksclr + arith + Multiply Scalar Double-FP Values + + + + + + 10 + + CVTPS2PD + Vpd + Wps + + sse2 + pcksclr + conver + Convert Packed Single-FP Values to Double-FP Values + + + + 66 + 10 + + CVTPD2PS + Vps + Wpd + + sse2 + pcksclr + conver + Convert Packed Double-FP Values to Single-FP Values + + + + F3 + 10 + + CVTSS2SD + Vsd + Wss + + sse2 + pcksclr + conver + Convert Scalar Single-FP Value to Scalar Double-FP Value + + + + F2 + 10 + + CVTSD2SS + Vss + Wsd + + sse2 + pcksclr + conver + Convert Scalar Double-FP Value to Scalar Single-FP Value + + + + + + 10 + + CVTDQ2PS + Vps + Wdq + + sse2 + pcksp + Convert Packed DW Integers to Single-FP Values + + + + 66 + 10 + + CVTPS2DQ + Vdq + Wps + + sse2 + pcksp + Convert Packed Single-FP Values to DW Integers + + + + F3 + 10 + + CVTTPS2DQ + Vdq + Wps + + sse2 + pcksp + Convert with Trunc. Packed Single-FP Values to DW Integers + + + + + + 09 + + SUBPS + Vps + Wps + + sse1 + simdfp + arith + Subtract Packed Single-FP Values + + + + F3 + 09 + + SUBSS + Vss + Wss + + sse1 + simdfp + arith + Subtract Scalar Single-FP Values + + + + 66 + 10 + + SUBPD + Vpd + Wpd + + sse2 + pcksclr + arith + Subtract Packed Double-FP Values + + + + F2 + 10 + + SUBSD + Vsd + Wsd + + sse2 + pcksclr + arith + Subtract Scalar Double-FP Values + + + + + + 09 + + MINPS + Vps + Wps + + sse1 + simdfp + arith + Return Minimum Packed Single-FP Values + + + + F3 + 09 + + MINSS + Vss + Wss + + sse1 + simdfp + arith + Return Minimum Scalar Single-FP Value + + + + 66 + 10 + + MINPD + Vpd + Wpd + + sse2 + pcksclr + arith + Return Minimum Packed Double-FP Values + + + + F2 + 10 + + MINSD + Vsd + Wsd + + sse2 + pcksclr + arith + Return Minimum Scalar Double-FP Value + + + + + + 09 + + DIVPS + Vps + Wps + + sse1 + simdfp + arith + Divide Packed Single-FP Values + + + + F3 + 09 + + DIVSS + Vss + Wss + + sse1 + simdfp + arith + Divide Scalar Single-FP Values + + + + 66 + 10 + + DIVPD + Vpd + Wpd + + sse2 + pcksclr + arith + Divide Packed Double-FP Values + + + + F2 + 10 + + DIVSD + Vsd + Wsd + + sse2 + pcksclr + arith + Divide Scalar Double-FP Values + + + + + + 09 + + MAXPS + Vps + Wps + + sse1 + simdfp + arith + Return Maximum Packed Single-FP Values + + + + F3 + 09 + + MAXSS + Vss + Wss + + sse1 + simdfp + arith + Return Maximum Scalar Single-FP Value + + + + 66 + 10 + + MAXPD + Vpd + Wpd + + sse2 + pcksclr + arith + Return Maximum Packed Double-FP Values + + + + F2 + 10 + + MAXSD + Vsd + Wsd + + sse2 + pcksclr + arith + Return Maximum Scalar Double-FP Value + + + + + + 06 + + PUNPCKLBW + Pq + Qd + + mmx + unpack + Unpack Low Data + + + 66 + 10 + + PUNPCKLBW + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 06 + + PUNPCKLWD + Pq + Qd + + mmx + unpack + Unpack Low Data + + + 66 + 10 + + PUNPCKLWD + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 06 + + PUNPCKLDQ + Pq + Qd + + mmx + unpack + Unpack Low Data + + + 66 + 10 + + PUNPCKLDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 06 + + PACKSSWB + Pq + Qd + + mmx + conver + Pack with Signed Saturation + + + 66 + 10 + + PACKSSWB + Vdq + Wdq + + sse2 + simdint + conver + Pack with Signed Saturation + + + + + + 06 + + PCMPGTB + Pq + Qd + + mmx + compar + Compare Packed Signed Integers for Greater Than + + + 66 + 10 + + PCMPGTB + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Signed Integers for Greater Than + + + + + + 06 + + PCMPGTW + Pq + Qd + + mmx + compar + Compare Packed Signed Integers for Greater Than + + + 66 + 10 + + PCMPGTW + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Signed Integers for Greater Than + + + + + + 06 + + PCMPGTD + Pq + Qd + + mmx + compar + Compare Packed Signed Integers for Greater Than + + + 66 + 10 + + PCMPGTD + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Signed Integers for Greater Than + + + + + + 06 + + PACKUSWB + Pq + Qq + + mmx + conver + Pack with Unsigned Saturation + + + 66 + 10 + + PACKUSWB + Vdq + Wdq + + sse2 + simdint + conver + Pack with Unsigned Saturation + + + + + + 06 + + PUNPCKHBW + Pq + Qq + + mmx + unpack + Unpack High Data + + + 66 + 10 + + PUNPCKHBW + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + PUNPCKHWD + Pq + Qq + + mmx + unpack + Unpack High Data + + + 66 + 10 + + PUNPCKHWD + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + PUNPCKHDQ + Pq + Qq + + mmx + unpack + Unpack High Data + + + 66 + 10 + + PUNPCKHDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + PACKSSDW + Pq + Qq + + mmx + conver + Pack with Signed Saturation + + + 66 + 10 + + PACKSSDW + Vdq + Wdq + + sse2 + simdint + conver + Pack with Signed Saturation + + + + + + 66 + 10 + + PUNPCKLQDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack Low Data + + + + + + 66 + 10 + + PUNPCKHQDQ + Vdq + Wdq + + sse2 + simdint + shunpck + Unpack High Data + + + + + + 06 + + MOVD + Pq + Ed + + mmx + datamov + Move Doubleword + + + + 10 + + MOVD + Pq + Ed + + + MOVQ + Pq + Eqp + + mmx + datamov + Move Doubleword/Quadword + + + + 66 + 10 + + MOVD + Vdq + Ed + + sse2 + simdint + datamov + Move Doubleword + + + + 66 + 10 + + MOVD + Vdq + Ed + + + MOVQ + Vdq + Eqp + + sse2 + simdint + datamov + Move Doubleword/Quadword + + + + + + 06 + + MOVQ + Pq + Qq + + mmx + datamov + Move Quadword + + + + 66 + 10 + + MOVDQA + Vdq + Wdq + + sse2 + simdint + datamov + Move Aligned Double Quadword + + + + F3 + 10 + + MOVDQU + Vdq + Wdq + + sse2 + simdint + datamov + Move Unaligned Double Quadword + + + + + + 09 + + PSHUFW + Pq + Qq + Ib + + sse1 + simdint + Shuffle Packed Words + + + + F2 + 10 + + PSHUFLW + Vdq + Wdq + Ib + + sse2 + simdint + shunpck + Shuffle Packed Low Words + + + + F3 + 10 + + PSHUFHW + Vdq + Wdq + Ib + + sse2 + simdint + shunpck + Shuffle Packed High Words + + + + 66 + 10 + + PSHUFD + Vdq + Wdq + Ib + + sse2 + simdint + shunpck + Shuffle Packed Doublewords + + + + + + 2 + 06 + + PSRLW + Nq + Ib + + mmx + shift + Shift Packed Data Right Logical + + + 2 + 66 + 10 + + PSRLW + Udq + Ib + + sse2 + shift + Shift Packed Data Right Logical + + + + 4 + 06 + + PSRAW + Nq + Ib + + mmx + shift + Shift Packed Data Right Arithmetic + + + 4 + 66 + 10 + + PSRAW + Udq + Ib + + sse2 + shift + Shift Packed Data Right Arithmetic + + + + 6 + 06 + + PSLLW + Nq + Ib + + mmx + shift + Shift Packed Data Left Logical + + + 6 + 66 + 10 + + PSLLW + Udq + Ib + + sse2 + shift + Shift Packed Data Left Logical + + + + + + 2 + 06 + + PSRLD + Nq + Ib + + mmx + shift + Shift Double Quadword Right Logical + + + 2 + 66 + 10 + + PSRLD + Udq + Ib + + sse2 + shift + Shift Double Quadword Right Logical + + + + 4 + 06 + + PSRAD + Nq + Ib + + mmx + shift + Shift Packed Data Right Arithmetic + + + 4 + 66 + 10 + + PSRAD + Udq + Ib + + sse2 + shift + Shift Packed Data Right Arithmetic + + + + 6 + 06 + + PSLLD + Nq + Ib + + mmx + shift + Shift Packed Data Left Logical + + + 6 + 66 + 10 + + PSLLD + Udq + Ib + + sse2 + shift + Shift Packed Data Left Logical + + + + + + 2 + 06 + + PSRLQ + Nq + Ib + + mmx + shift + Shift Packed Data Right Logical + + + 2 + 66 + 10 + + PSRLQ + Udq + Ib + + sse2 + shift + Shift Packed Data Right Logical + + + + + 3 + 66 + 10 + + PSRLDQ + Udq + Ib + + sse2 + simdint + shift + Shift Double Quadword Right Logical + + + + 6 + 06 + + PSLLQ + Nq + Ib + + mmx + shift + Shift Packed Data Left Logical + + + 6 + 66 + 10 + + PSLLQ + Udq + Ib + + sse2 + shift + Shift Packed Data Left Logical + + + + + 7 + 66 + 10 + + PSLLDQ + Udq + Ib + + sse2 + simdint + shift + Shift Double Quadword Left Logical + + + + + + 06 + + PCMPEQB + Pq + Qq + + mmx + compar + Compare Packed Data for Equal + + + + 66 + 10 + + PCMPEQB + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Data for Equal + + + + + + 06 + + PCMPEQW + Pq + Qq + + mmx + compar + Compare Packed Data for Equal + + + + 66 + 10 + + PCMPEQW + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Data for Equal + + + + + + 06 + + PCMPEQD + Pq + Qq + + mmx + compar + Compare Packed Data for Equal + + + + 66 + 10 + + PCMPEQD + Vdq + Wdq + + sse2 + simdint + compar + Compare Packed Data for Equal + + + + + + 06 + + EMMS + + mmx + x87fpu + control + Empty MMX Technology State + + + + + + 10 + + VMREAD + Ed + Gd + + vmx + + oszapc + oszapc + + Read Field from Virtual-Machine Control Structure + Reads a specified VMCS field + + + + 10 + + VMREAD + Eq + Gq + + vmx + + oszapc + oszapc + + Read Field from Virtual-Machine Control Structure + Reads a specified VMCS field + + + + + + + 10 + + VMWRITE + Gd + Ed + + vmx + + oszapc + oszapc + + Write Field to Virtual-Machine Control Structure + Writes a specified VMCS field + + + + 10 + + VMWRITE + Gq + Eq + + vmx + + oszapc + oszapc + + Write Field to Virtual-Machine Control Structure + Writes a specified VMCS field + + + + + + + + + 66 + 10 + + HADDPD + Vpd + Wpd + + sse3 + simdfp + arith + Packed Double-FP Horizontal Add + + + + F2 + 10 + + HADDPS + Vps + Wps + + sse3 + simdfp + arith + Packed Single-FP Horizontal Add + + + + + + 66 + 10 + + HSUBPD + Vpd + Wpd + + sse3 + simdfp + arith + Packed Double-FP Horizontal Subtract + + + + + F2 + 10 + + HSUBPS + Vps + Wps + + sse3 + simdfp + arith + Packed Single-FP Horizontal Subtract + + + + + + 06 + + MOVD + Ed + Pq + + mmx + datamov + Move Doubleword + + + + 10 + + MOVD + Ed + Pq + + + MOVQ + Eqp + Pq + + mmx + datamov + Move Doubleword/Quadword + + + + 66 + 10 + + MOVD + Ed + Vdq + + sse2 + simdint + datamov + Move Doubleword + + + + 66 + 10 + + MOVD + Ed + Vdq + + + MOVQ + Eqp + Edq + + sse2 + simdint + datamov + Move Doubleword/Quadword + + + + F3 + 10 + + MOVQ + Vq + Wq + + sse2 + simdint + datamov + Move Quadword + + + + + + 06 + + MOVQ + Qq + Pq + + mmx + datamov + Move Quadword + + + + 66 + 10 + + MOVDQA + Wdq + Vdq + + sse2 + simdint + datamov + Move Aligned Double Quadword + + + + F3 + 10 + + MOVDQU + Wdq + Vdq + + sse2 + simdint + datamov + Move Unaligned Double Quadword + + + + + + 03 + JOJvds + genbranchcond + o + Jump short if overflow (OF=1) + + + + + + 03 + JNOJvds + genbranchcond + o + Jump short if not overflow (OF=0) + + + + + + 03 + JBJvds + JNAEJvds + JCJvds + genbranchcond + c + Jump short if below/not above or equal/carry (CF=1) + + + + + + 03 + JNBJvds + JAEJvds + JNCJvds + genbranchcond + c + Jump short if not below/above or equal/not carry (CF=0) + + + + + + 03 + JZJvds + JEJvds + genbranchcond + z + Jump short if zero/equal (ZF=0) + + + + + + 03 + JNZJvds + JNEJvds + genbranchcond + z + Jump short if not zero/not equal (ZF=1) + + + + + + 03 + JBEJvds + JNAJvds + genbranchcond + + zc + Jump short if below or equal/not above (CF=1 AND ZF=1) + + + + + + 03 + JNBEJvds + JAJvds + genbranchcond + + zc + Jump short if not below or equal/above (CF=0 AND ZF=0) + + + + + + 03 + JSJvds + genbranchcond + s + Jump short if sign (SF=1) + + + + + + 03 + JNSJvds + genbranchcond + s + Jump short if not sign (SF=0) + + + + + + 03 + JPJvds + JPEJvds + genbranchcond + p + Jump short if parity/parity even (PF=1) + + + + + + 03 + JNPJvds + JPOJvds + genbranchcond + p + Jump short if not parity/parity odd + + + + + + 03 + JLJvds + JNGEJvds + genbranchcond + os + Jump short if less/not greater (SF!=OF) + + + + + + 03 + JNLJvds + JGEJvds + genbranchcond + os + Jump short if not less/greater or equal (SF=OF) + + + + + + 03 + JLEJvds + JNGJvds + genbranchcond + osz + Jump short if less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + 03 + JNLEJvds + JGJvds + genbranchcond + osz + Jump short if not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 0 + 03 + SETOEb + gendatamov + o + Set Byte on Condition - overflow (OF=1) + + + + + + 0 + 03 + SETNOEb + gendatamov + o + Set Byte on Condition - not overflow (OF=0) + + + + + + 0 + 03 + SETBEb + SETNAEEb + SETCEb + gendatamov + c + Set Byte on Condition - below/not above or equal/carry (CF=1) + + + + + + 0 + 03 + SETNBEb + SETAEEb + SETNCEb + gendatamov + c + Set Byte on Condition - not below/above or equal/not carry (CF=0) + + + + + + 0 + 03 + SETZEb + SETEEb + gendatamov + z + Set Byte on Condition - zero/equal (ZF=0) + + + + + + 0 + 03 + SETNZEb + SETNEEb + gendatamov + z + Set Byte on Condition - not zero/not equal (ZF=1) + + + + + + 0 + 03 + SETBEEb + SETNAEb + gendatamov + + zc + Set Byte on Condition - below or equal/not above (CF=1 AND ZF=1) + + + + + + 0 + 03 + SETNBEEb + SETAEb + gendatamov + + zc + Set Byte on Condition - not below or equal/above (CF=0 AND ZF=0) + + + + + + 0 + 03 + SETSEb + gendatamov + s + Set Byte on Condition - sign (SF=1) + + + + + + 0 + 03 + SETNSEb + gendatamov + s + Set Byte on Condition - not sign (SF=0) + + + + + + 0 + 03 + SETPEb + SETPEEb + gendatamov + p + Set Byte on Condition - parity/parity even (PF=1) + + + + + + 0 + 03 + SETNPEb + SETPOEb + gendatamov + p + Set Byte on Condition - not parity/parity odd + + + + + + 0 + 03 + SETLEb + SETNGEEb + gendatamov + os + Set Byte on Condition - less/not greater (SF!=OF) + + + + + + 0 + 03 + SETNLEb + SETGEEb + gendatamov + os + Set Byte on Condition - not less/greater or equal (SF=OF) + + + + + + 0 + 03 + SETLEEb + SETNGEb + gendatamov + osz + Set Byte on Condition - less or equal/not greater ((ZF=1) OR (SF!=OF)) + + + + + + 0 + 03 + SETNLEEb + SETGEb + gendatamov + osz + Set Byte on Condition - not less nor equal/greater ((ZF=0) AND (SF=OF)) + + + + + + 03 + + PUSH + SS:[rSP] + FS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 03 + + POP + FS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + + + + 04 + + CPUID + IA32_BIOS_SIGN_ID + EAX + ECX + EDX + EBX + + gencontrol + CPU Identification + + + + + + 03 + BTEvqpGvqp + genbit + oszapccoszap + Bit Test + + + + + + 03 + + SHLD + Evqp + Gvqp + Ib + + genshftrot + oszapcoszpcoac + Double Precision Shift Left + + + + + + 03 + + SHLD + Evqp + Gvqp + CL + + genshftrot + oszapcoszpcoac + Double Precision Shift Left + + + + + + + + 03 + + PUSH + SS:[rSP] + GS + + genstacksegreg + Push Word, Doubleword or Quadword Onto the Stack + + + + + + 03 + + POP + GS + SS:[rSP] + + genstacksegreg + Pop a Value from the Stack + + + + + + 03 + + RSM + Flags + + systembranch + + Resume from System Management Mode + + + + + + 03 + BTSEvqpGvqp + genbit + oszapccoszap + Bit Test and Set + + + + + + 03 + SHRDEvqpGvqpIb + genshftrot + oszapcoszpcoac + Double Precision Shift Right + + + + + + 03 + + SHRD + Evqp + Gvqp + CL + + genshftrot + oszapcoszpcoac + Double Precision Shift Right + + + + + + + + + 0 + 08 + + FXSAVE + Mstx + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + + sm + Save x87 FPU, MMX, XMM, and MXCSR State + + + + 0 + 10 + + FXSAVE + Mstx + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + + sm + Save x87 FPU, MMX, XMM, and MXCSR State + + + + + 1 + 08 + + FXRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + Mstx + + sm + Restore x87 FPU, MMX, XMM, and MXCSR State + + + + 1 + 10 + + FXRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + Mstx + + sm + Restore x87 FPU, MMX, XMM, and MXCSR State + + + + 2 + 09 + + LDMXCSR + Md + + sse1 + mxcsrsm + Load MXCSR Register + + + + 3 + 09 + + STMXCSR + Md + + sse1 + mxcsrsm + Store MXCSR Register State + + + + 4 + 12 + + + XSAVE + M + EDX + EAX + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + + system + + Save Processor Extended States + Save processor extended states to memory. The states are specified by EDX:EAX + + + + 4 + 12 + + + XSAVE + M + EDX + EAX + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + + system + + Save Processor Extended States + Save processor extended states to memory. The states are specified by EDX:EAX + + + + + 5 + 10 + + LFENCE + + sse2 + order + Load Fence + + + 5 + 12 + + + XRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + M + EDX + EAX + + system + + Restore Processor Extended States + Restore processor extended states from memory. The states are specified by EDX:EAX + + + + 5 + 12 + + + XRSTOR + ST + ST1 + ST2 + ST3 + ST4 + ST5 + ST6 + ST7 + MMX0 + MMX1 + MMX2 + MMX3 + MMX4 + MMX5 + MMX6 + MMX7 + XMM0 + XMM1 + XMM2 + XMM3 + XMM4 + XMM5 + XMM6 + XMM7 + XMM8 + XMM9 + XMM10 + XMM11 + XMM12 + XMM13 + XMM14 + XMM15 + M + EDX + EAX + + system + + Restore Processor Extended States + Restore processor extended states from memory. The states are specified by EDX:EAX + + + + + 6 + 10 + + MFENCE + + sse2 + order + Memory Fence + + + + 7 + 09 + + SFENCE + + sse1 + order + Store Fence + + + 7 + 10 + + CLFLUSH + Mb + + sse2 + cachect + Flush Cache Line + + + + + + 03 + IMULGvqpEvqp + genarithbinary + oszapcocszap + Signed Multiply + + + + + + 04 + + CMPXCHG + Eb + AL + Gb + + gen + datamov + arith + binary + oszapcoszapc + Compare and Exchange + + + + + + 04 + + CMPXCHG + Evqp + rAX + Gvqp + + gen + datamov + arith + binary + oszapcoszapc + Compare and Exchange + + + + + + 03 + + LSS + SS + Gvqp + Mptp + + gen + datamovsegreg + Load Far Pointer + + + + + + 03 + BTREvqpGvqp + genbit + oszapccoszap + Bit Test and Reset + + + + + + + 03 + + LFS + FS + Gvqp + Mptp + + gen + datamovsegreg + Load Far Pointer + + + + + + + 03 + + LGS + GS + Gvqp + Mptp + + gen + datamovsegreg + Load Far Pointer + + + + + + 03 + MOVZXGvqpEb + genconver + Move with Zero-Extend + + + + + + 03 + MOVZXGvqpEw + genconver + Move with Zero-Extend + + + + + + 99 + JMPE + systembranch + Jump to IA-64 Instruction Set + + + + F3 + 12 + + POPCNT + Gvqp + Evqp + + gen + bit + oszapc + osapc + + Bit Population Count + Count the 1s in op2 + + + + + + + 02 + + UD + G + E + + gencontrol + Undefined Instruction + + + + + 03 + + 4 + BTEvqpIb + genbit + oszapccoszap + Bit Test + + + 5 + BTSEvqpIb + genbit + oszapccoszap + Bit Test and Set + + + 6 + BTREvqpIb + genbit + oszapccoszap + Bit Test and Reset + + + 7 + BTCEvqpIb + genbit + oszapccoszap + Bit Test and Complement + + + + + + 03 + BTCEvqpGvqp + genbit + oszapccoszap + Bit Test and Complement + + + + + + 03 + BSFGvqpEvqp + genbit + oszapczosapc + Bit Scan Forward + + + + + + 03 + BSRGvqpEvqp + genbit + oszapczosapc + Bit Scan Reverse + + + + + + 03 + MOVSXGvqpEb + genconver + Move with Sign-Extension + + + + + + 03 + MOVSXGvqpEw + genconver + Move with Sign-Extension + + + + + + 04 + XADDEbGb + gen + datamovarith + binary + oszapcoszapc + Exchange and Add + + + + + + 04 + XADDEvqpGvqp + gen + datamovarith + binary + oszapcoszapc + Exchange and Add + + + + + + + + 09 + + CMPPS + Vps + Wps + Ib + + sse1 + simdfp + compar + Compare Packed Single-FP Values + + + + F3 + 09 + + CMPSS + Vss + Wss + Ib + + sse1 + simdfp + compar + Compare Scalar Single-FP Values + + + + 66 + 10 + + CMPPD + Vpd + Wpd + Ib + + sse2 + pcksclr + compar + Compare Packed Double-FP Values + + + + F2 + 10 + + CMPSD + Vsd + Wsd + Ib + + sse2 + pcksclr + compar + Compare Scalar Double-FP Values + + + + + + + + 10 + + MOVNTI + Mdqp + Gdqp + + sse2 + cachect + Store Doubleword Using Non-Temporal Hint + + + + + + + + + 09 + + PINSRW + Pq + Rdqp + Ib + + + PINSRW + Pq + Mw + Ib + + sse1 + simdint + + Insert Word + + + + 66 + 09 + + PINSRW + Vdq + Rdqp + Ib + + + PINSRW + Vdq + Mw + Ib + + sse1 + simdint + + Insert Word + + + + + + + + + 09 + + PEXTRW + Gdqp + Nq + Ib + + sse1 + simdint + + Extract Word + + + + + 66 + 09 + + PEXTRW + Gdqp + Udq + Ib + + sse1 + simdint + + Extract Word + + + + + + + + 09 + + SHUFPS + Vps + Wps + Ib + + sse1 + simdfp + shunpck + Shuffle Packed Single-FP Values + + + + 66 + 10 + + SHUFPD + Vpd + Wpd + Ib + + sse2 + pcksclr + shunpck + Shuffle Packed Double-FP Values + + + + + + + + 1 + 05 + + CMPXCHG8B + Mq + EAX + EDX + EBX + ECX + + gen + datamovarith + binary + zz + Compare and Exchange Bytes + + + + 1 + 10 + + CMPXCHG8B + Mq + + EAX + EDX + EBX + ECX + + + CMPXCHG16B + Mdq + RAX + RDX + RBX + RCX + + gen + datamovarithbinary + zz + Compare and Exchange Bytes + + + + 6 + 10 + + VMPTRLD + Mq + + vmx + + oszapc + oszapc + + Load Pointer to Virtual-Machine Control Structure + Loads the current VMCS pointer from memory + + + + 66 + 6 + 10 + + VMCLEAR + Mq + + vmx + + oszapc + oszapc + + Clear Virtual-Machine Control Structure + Copy VMCS data to VMCS region in memory + + + + F3 + 6 + 10 + + VMXON + Mq + + vmx + + oszapc + oszapc + + Enter VMX Operation + Enter VMX root operation + + + + + 7 + 10 + + VMPTRST + Mq + + vmx + + oszapc + oszapc + + Store Pointer to Virtual-Machine Control Structure + Stores the current VMCS pointer into memory + + + + + + + + 04 + BSWAPZvqp + gendatamov + Byte Swap + + + + + + 66 + 10 + + ADDSUBPD + Vpd + Wpd + + sse3 + simdfp + arith + Packed Double-FP Add/Subtract + + + + F2 + 10 + + ADDSUBPS + Vps + Wps + + sse3 + simdfp + arith + Packed Single-FP Add/Subtract + + + + + + 06 + + PSRLW + Pq + Qq + + mmx + shift + Shift Packed Data Right Logical + + + 66 + 10 + + PSRLW + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Logical + + + + + + 06 + + PSRLD + Pq + Qq + + mmx + shift + Shift Packed Data Right Logical + + + 66 + 10 + + PSRLD + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Logical + + + + + + 06 + + PSRLQ + Pq + Qq + + mmx + shift + Shift Packed Data Right Logical + + + 66 + 10 + + PSRLQ + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Logical + + + + + + 06 + + PADDQ + Pq + Qq + + sse2 + simdint + arith + Add Packed Quadword Integers + + + + 66 + 10 + + PADDQ + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Quadword Integers + + + + + + 06 + + PMULLW + Pq + Qq + + mmx + arith + Multiply Packed Signed Integers and Store Low Result + + + 66 + 10 + + PMULLW + Vdq + Wdq + + sse2 + simdint + arith + Multiply Packed Signed Integers and Store Low Result + + + + + + 66 + 10 + + MOVQ + Wq + Vq + + sse2 + simdint + datamov + Move Quadword + + + + F3 + 10 + + MOVQ2DQ + Vdq + Nq + + sse2 + simdint + datamov + Move Quadword from MMX Technology to XMM Register + + + + F2 + 10 + + MOVDQ2Q + Pq + Uq + + sse2 + simdint + datamov + Move Quadword from XMM to MMX Technology Register + + + + + + 09 + + PMOVMSKB + Gdqp + Nq + + sse1 + simdint + Move Byte Mask + + + + 66 + 09 + + PMOVMSKB + Gdqp + Udq + + sse1 + simdint + Move Byte Mask + + + + + + 06 + + PSUBUSB + Pq + Qq + + mmx + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + 66 + 10 + + PSUBUSB + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + + + + 06 + + PSUBUSW + Pq + Qq + + mmx + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + 66 + 06 + + PSUBUSW + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Unsigned Integers with Unsigned Saturation + + + + + + 09 + + PMINUB + Pq + Qq + + sse1 + simdint + Minimum of Packed Unsigned Byte Integers + + + + 66 + 09 + + PMINUB + Vdq + Wdq + + sse1 + simdint + Minimum of Packed Unsigned Byte Integers + + + + + + 06 + + PAND + Pq + Qd + + mmx + logical + Logical AND + + + 66 + 10 + + PAND + Vdq + Wdq + + sse2 + simdint + logical + Logical AND + + + + + + 06 + + PADDUSB + Pq + Qq + + mmx + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + 66 + 10 + + PADDUSB + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + + + + 06 + + PADDUSW + Pq + Qq + + mmx + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + 66 + 10 + + PADDUSW + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Unsigned Integers with Unsigned Saturation + + + + + + 09 + + PMAXUB + Pq + Qq + + sse1 + simdint + Maximum of Packed Unsigned Byte Integers + + + + 66 + 09 + + PMAXUB + Vdq + Wdq + + sse1 + simdint + Maximum of Packed Unsigned Byte Integers + + + + + + 06 + + PANDN + Pq + Qq + + mmx + logical + Logical AND NOT + + + 66 + 10 + + PANDN + Vdq + Wdq + + sse2 + simdint + logical + Logical AND NOT + + + + + + 09 + + PAVGB + Pq + Qq + + sse1 + simdint + Average Packed Integers + + + + 66 + 09 + + PAVGB + Vdq + Wdq + + sse1 + simdint + Average Packed Integers + + + + + + 06 + + PSRAW + Pq + Qq + + mmx + shift + Shift Packed Data Right Arithmetic + + + 66 + 10 + + PSRAW + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Arithmetic + + + + + + 06 + + PSRAD + Pq + Qq + + mmx + shift + Shift Packed Data Right Arithmetic + + + 66 + 10 + + PSRAD + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Right Arithmetic + + + + + + 09 + + PAVGW + Pq + Qq + + sse1 + simdint + Average Packed Integers + + + + 66 + 09 + + PAVGW + Vdq + Wdq + + sse1 + simdint + Average Packed Integers + + + + + + 09 + + PMULHUW + Pq + Qq + + sse1 + simdint + Multiply Packed Unsigned Integers and Store High Result + + + + 66 + 09 + + PMULHUW + Vdq + Wdq + + sse1 + simdint + Multiply Packed Unsigned Integers and Store High Result + + + + + + 06 + + PMULHW + Pq + Qq + + mmx + arith + Multiply Packed Signed Integers and Store High Result + + + 66 + 10 + + PMULHW + Vdq + Wdq + + sse2 + simdint + arith + Multiply Packed Signed Integers and Store High Result + + + + + + F2 + 10 + + CVTPD2DQ + Vdq + Wpd + + sse2 + pcksclr + conver + Convert Packed Double-FP Values to DW Integers + + + + 66 + 10 + + CVTTPD2DQ + Vdq + Wpd + + sse2 + pcksclr + conver + Convert with Trunc. Packed Double-FP Values to DW Integers + + + + F3 + 10 + + CVTDQ2PD + Vpd + Wdq + + sse2 + pcksclr + conver + Convert Packed DW Integers to Double-FP Values + + + + + + 09 + + MOVNTQ + Mq + Pq + + sse1 + cachect + Store of Quadword Using Non-Temporal Hint + + + + 66 + 10 + + MOVNTDQ + Mdq + Vdq + + sse2 + cachect + Store Double Quadword Using Non-Temporal Hint + + + + + + 06 + + PSUBSB + Pq + Qq + + mmx + arith + Subtract Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PSUBSB + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Signed Integers with Signed Saturation + + + + + + 06 + + PSUBSW + Pq + Qq + + mmx + arith + Subtract Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PSUBSW + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Signed Integers with Signed Saturation + + + + + + 09 + + PMINSW + Pq + Qq + + sse1 + simdint + Minimum of Packed Signed Word Integers + + + + 66 + 09 + + PMINSW + Vdq + Wdq + + sse1 + simdint + Minimum of Packed Signed Word Integers + + + + + + 06 + + POR + Pq + Qq + + mmx + logical + Bitwise Logical OR + + + 66 + 10 + + POR + Vdq + Wdq + + sse2 + simdint + logical + Bitwise Logical OR + + + + + + 06 + + PADDSB + Pq + Qq + + mmx + arith + Add Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PADDSB + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Signed Integers with Signed Saturation + + + + + + 06 + + PADDSW + Pq + Qq + + mmx + arith + Add Packed Signed Integers with Signed Saturation + + + 66 + 10 + + PADDSW + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Signed Integers with Signed Saturation + + + + + + 09 + + PMAXSW + Pq + Qq + + sse1 + simdint + Maximum of Packed Signed Word Integers + + + + 66 + 09 + + PMAXSW + Vdq + Wdq + + sse1 + simdint + Maximum of Packed Signed Word Integers + + + + + + 06 + + PXOR + Pq + Qq + + mmx + logical + Logical Exclusive OR + + + 66 + 10 + + PXOR + Vdq + Wdq + + sse2 + simdint + logical + Logical Exclusive OR + + + + + + F2 + 10 + + LDDQU + Vdq + Mdq + + sse3 + cachect + Load Unaligned Integer 128 Bits + + + + + + 06 + + PSLLW + Pq + Qq + + mmx + shift + Shift Packed Data Left Logical + + + 66 + 10 + + PSLLW + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Left Logical + + + + + + 06 + + PSLLD + Pq + Qq + + mmx + shift + Shift Packed Data Left Logical + + + 66 + 10 + + PSLLD + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Left Logical + + + + + + 06 + + PSLLQ + Pq + Qq + + mmx + shift + Shift Packed Data Left Logical + + + 66 + 10 + + PSLLQ + Vdq + Wdq + + sse2 + simdint + shift + Shift Packed Data Left Logical + + + + + + 10 + + PMULUDQ + Pq + Qq + + sse2 + simdint + arith + Multiply Packed Unsigned DW Integers + + + + 66 + 10 + + PMULUDQ + Vdq + Wdq + + sse2 + simdint + arith + Multiply Packed Unsigned DW Integers + + + + + + 06 + + PMADDWD + Pq + Qd + + mmx + arith + Multiply and Add Packed Integers + + + 66 + 10 + + PMADDWD + Vdq + Wdq + + sse2 + simdint + arith + Multiply and Add Packed Integers + + + + + + 09 + + PSADBW + Pq + Qq + + sse1 + simdint + Compute Sum of Absolute Differences + + + + 66 + 09 + + PSADBW + Vdq + Wdq + + sse1 + simdint + Compute Sum of Absolute Differences + + + + + + 09 + + MASKMOVQ + (DS:)[rDI] + Pq + Nq + + sse1 + cachect + Store Selected Bytes of Quadword + + + + 66 + 10 + + MASKMOVDQU + (DS:)[rDI] + Vdq + Udq + + sse2 + cachect + Store Selected Bytes of Double Quadword + + + + + + 06 + + PSUBB + Pq + Qq + + mmx + arith + Subtract Packed Integers + + + 66 + 10 + + PSUBB + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Integers + + + + + + 06 + + PSUBW + Pq + Qq + + mmx + arith + Subtract Packed Integers + + + 66 + 10 + + PSUBW + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Integers + + + + + + 06 + + PSUBD + Pq + Qq + + mmx + arith + Subtract Packed Integers + + + 66 + 10 + + PSUBD + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Integers + + + + + + 10 + + PSUBQ + Pq + Qq + + sse2 + simdint + arith + Subtract Packed Quadword Integers + + + + 66 + 10 + + PSUBQ + Vdq + Wdq + + sse2 + simdint + arith + Subtract Packed Quadword Integers + + + + + + 06 + + PADDB + Pq + Qq + + mmx + arith + Add Packed Integers + + + 66 + 10 + + PADDB + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Integers + + + + + + 06 + + PADDW + Pq + Qq + + mmx + arith + Add Packed Integers + + + 66 + 10 + + PADDW + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Integers + + + + + + 06 + + PADDD + Pq + Qq + + mmx + arith + Add Packed Integers + + + 66 + 10 + + PADDD + Vdq + Wdq + + sse2 + simdint + arith + Add Packed Integers + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +