Added comments and clarification on the PIC and PIT emulation code.
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34
CMOS.js
34
CMOS.js
@ -4,22 +4,34 @@
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Original is Copyright (c) 2011-2012 Fabrice Bellard
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Original is Copyright (c) 2011-2012 Fabrice Bellard
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Redistribution or commercial use is prohibited without the author's permission.
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Redistribution or commercial use is prohibited without the author's permission.
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Clock Emulator
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CMOS Ram Memory, actually just the RTC Clock Emulator
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Useful references:
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------------------
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http://www.bioscentral.com/misc/cmosmap.htm
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http://wiki.osdev.org/CMOS
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*/
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*/
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function formatter(a) { return ((a / 10) << 4) | (a % 10);}
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/*
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In this implementation, bytes are stored in the RTC in BCD format
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binary -> bcd: bcd = ((bin / 10) << 4) | (bin % 10)
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bcd -> binary: bin = ((bcd / 16) * 10) + (bcd & 0xf)
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*/
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function bin_to_bcd(a) { return ((a / 10) << 4) | (a % 10);}
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function CMOS(PC) {
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function CMOS(PC) {
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var time_array, d;
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var time_array, d;
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time_array = new Uint8Array(128);
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time_array = new Uint8Array(128);
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this.cmos_data = time_array;
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this.cmos_data = time_array;
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this.cmos_index = 0;
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this.cmos_index = 0;
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d = new Date();
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d = new Date();
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time_array[0] = formatter(d.getUTCSeconds());
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time_array[0] = bin_to_bcd(d.getUTCSeconds());
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time_array[2] = formatter(d.getUTCMinutes());
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time_array[2] = bin_to_bcd(d.getUTCMinutes());
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time_array[4] = formatter(d.getUTCHours());
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time_array[4] = bin_to_bcd(d.getUTCHours());
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time_array[6] = formatter(d.getUTCDay());
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time_array[6] = bin_to_bcd(d.getUTCDay());
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time_array[7] = formatter(d.getUTCDate());
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time_array[7] = bin_to_bcd(d.getUTCDate());
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time_array[8] = formatter(d.getUTCMonth() + 1);
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time_array[8] = bin_to_bcd(d.getUTCMonth() + 1);
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time_array[9] = formatter(d.getUTCFullYear() % 100);
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time_array[9] = bin_to_bcd(d.getUTCFullYear() % 100);
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time_array[10] = 0x26;
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time_array[10] = 0x26;
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time_array[11] = 0x02;
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time_array[11] = 0x02;
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time_array[12] = 0x00;
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time_array[12] = 0x00;
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@ -30,7 +42,7 @@ function CMOS(PC) {
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}
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}
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CMOS.prototype.ioport_write = function(mem8_loc, data) {
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CMOS.prototype.ioport_write = function(mem8_loc, data) {
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if (mem8_loc == 0x70) {
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if (mem8_loc == 0x70) {
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// the high order bit is used to indicate NMI masking
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// the high order bit is used to indicate NMI masking
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// low order bits are used to address CMOS
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// low order bits are used to address CMOS
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// the index written here is used on an ioread 0x71
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// the index written here is used on an ioread 0x71
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this.cmos_index = data & 0x7f;
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this.cmos_index = data & 0x7f;
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@ -41,7 +53,7 @@ CMOS.prototype.ioport_read = function(mem8_loc) {
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if (mem8_loc == 0x70) {
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if (mem8_loc == 0x70) {
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return 0xff;
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return 0xff;
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} else {
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} else {
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// else here => 0x71, i.e., CMOS read
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// else here => 0x71, i.e., CMOS read
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data = this.cmos_data[this.cmos_index];
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data = this.cmos_data[this.cmos_index];
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if (this.cmos_index == 10)
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if (this.cmos_index == 10)
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// flip the UIP (update in progress) bit on a read
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// flip the UIP (update in progress) bit on a read
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@ -7,25 +7,25 @@ Redistribution or commercial use is prohibited without the author's permission.
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Main PC Emulator Routine
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Main PC Emulator Routine
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*/
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*/
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// used as callback wrappers for emulated PIT and PIC chips
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function set_hard_irq_wrapper(irq) { this.hard_irq = irq;}
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function set_hard_irq_wrapper(irq) { this.hard_irq = irq;}
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function return_cycle_count() { return this.cycle_count; }
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function return_cycle_count() { return this.cycle_count; }
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function PCEmulator(uh) {
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function PCEmulator(params) {
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var cpu;
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var cpu;
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cpu = new CPU_X86();
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cpu = new CPU_X86();
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this.cpu = cpu;
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this.cpu = cpu;
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cpu.phys_mem_resize(uh.mem_size);
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cpu.phys_mem_resize(params.mem_size);
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this.init_ioports();
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this.init_ioports();
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this.register_ioport_write(0x80, 1, 1, this.ioport80_write);
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this.register_ioport_write(0x80, 1, 1, this.ioport80_write);
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this.pic = new PIC_Controller(this, 0x20, 0xa0, set_hard_irq_wrapper.bind(cpu));
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this.pic = new PIC_Controller(this, 0x20, 0xa0, set_hard_irq_wrapper.bind(cpu));
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this.pit = new PIT(this, this.pic.set_irq.bind(this.pic, 0), return_cycle_count.bind(cpu));
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this.pit = new PIT(this, this.pic.set_irq.bind(this.pic, 0), return_cycle_count.bind(cpu));
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this.cmos = new CMOS(this);
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this.cmos = new CMOS(this);
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this.serial = new Serial(this, 0x3f8, this.pic.set_irq.bind(this.pic, 4), uh.serial_write);
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this.serial = new Serial(this, 0x3f8, this.pic.set_irq.bind(this.pic, 4), params.serial_write);
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this.kbd = new KBD(this, this.reset.bind(this));
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this.kbd = new KBD(this, this.reset.bind(this));
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this.reset_request = 0;
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this.reset_request = 0;
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if (uh.clipboard_get && uh.clipboard_set) {
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if (params.clipboard_get && params.clipboard_set) {
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this.jsclipboard = new clipboard_device(this, 0x3c0, uh.clipboard_get, uh.clipboard_set, uh.get_boot_time);
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this.jsclipboard = new clipboard_device(this, 0x3c0, params.clipboard_get, params.clipboard_set, params.get_boot_time);
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}
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}
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cpu.ld8_port = this.ld8_port.bind(this);
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cpu.ld8_port = this.ld8_port.bind(this);
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cpu.ld16_port = this.ld16_port.bind(this);
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cpu.ld16_port = this.ld16_port.bind(this);
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@ -36,7 +36,7 @@ function PCEmulator(uh) {
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cpu.get_hard_intno = this.pic.get_hard_intno.bind(this.pic);
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cpu.get_hard_intno = this.pic.get_hard_intno.bind(this.pic);
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}
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}
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PCEmulator.prototype.load_binary = function(Gg, ha) { return this.cpu.load_binary(Gg, ha); };
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PCEmulator.prototype.load_binary = function(url, mem8_loc) { return this.cpu.load_binary(url, mem8_loc); };
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PCEmulator.prototype.start = function() { setTimeout(this.timer_func.bind(this), 10); };
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PCEmulator.prototype.start = function() { setTimeout(this.timer_func.bind(this), 10); };
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218
PIC.js
218
PIC.js
@ -1,11 +1,71 @@
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/*
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/*
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JSLinux-deobfuscated - An annotated version of the original JSLinux.
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JSLinux-deobfuscated - An annotated version of the original JSLinux.
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Original is Copyright (c) 2011-2012 Fabrice Bellard
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Original is Copyright (c) 2011-2012 Fabrice Bellard
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Redistribution or commercial use is prohibited without the author's permission.
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Redistribution or commercial use is prohibited without the author's permission.
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8259 PIC (Programmable Interrupt Controller) Emulation Code
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8259A PIC (Programmable Interrupt Controller) Emulation Code
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The 8259 combines multiple interrupt input sources into a single
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interrupt output to the host microprocessor, extending the interrupt
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levels available in a system beyond the one or two levels found on the
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processor chip.
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There are three registers, an Interrupt Mask Register (IMR), an
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Interrupt Request Register (IRR), and an In-Service Register
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(ISR):
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IRR - a mask of the current interrupts that are pending acknowledgement
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ISR - a mask of the interrupts that are pending an EOI
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IMR - a mask of interrupts that should not be sent an acknowledgement
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End Of Interrupt (EOI) operations support specific EOI, non-specific
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EOI, and auto-EOI. A specific EOI specifies the IRQ level it is
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acknowledging in the ISR. A non-specific EOI resets the IRQ level in
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the ISR. Auto-EOI resets the IRQ level in the ISR immediately after
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the interrupt is acknowledged.
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After the IBM XT, it was decided that 8 IRQs was not enough.
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The backwards-compatible solution was simply to chain two 8259As together,
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the master and slave PIC.
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Useful References
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-----------------
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https://en.wikipedia.org/wiki/Programmable_Interrupt_Controller
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https://en.wikipedia.org/wiki/Intel_8259
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http://www.thesatya.com/8259.html
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*/
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*/
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/*
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Common PC arrangements of IRQ lines:
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------------------------------------
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PC/AT and later systems had two 8259 controllers, master and
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slave. IRQ0 through IRQ7 are the master 8259's interrupt lines, while
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IRQ8 through IRQ15 are the slave 8259's interrupt lines. The labels on
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the pins on an 8259 are IR0 through IR7. IRQ0 through IRQ15 are the
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names of the ISA bus's lines to which the 8259s are attached.
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Master 8259
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IRQ0 – Intel 8253 or Intel 8254 Programmable Interval Timer, aka the system timer
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IRQ1 – Intel 8042 keyboard controller
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IRQ2 – not assigned in PC/XT; cascaded to slave 8259 INT line in PC/AT
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IRQ3 – 8250 UART serial ports 2 and 4
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IRQ4 – 8250 UART serial ports 1 and 3
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IRQ5 – hard disk controller in PC/XT; Intel 8255 parallel ports 2 and 3 in PC/AT
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IRQ6 – Intel 82072A floppy disk controller
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IRQ7 – Intel 8255 parallel port 1 / spurious interrupt
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Slave 8259 (PC/AT and later only)
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IRQ8 – real-time clock (RTC)
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IRQ9 – no common assignment, but 8-bit cards' IRQ2 line is routed to this interrupt.
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IRQ10 – no common assignment
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IRQ11 – no common assignment
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IRQ12 – Intel 8042 PS/2 mouse controller
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IRQ13 – math coprocessor
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IRQ14 – hard disk controller 1
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IRQ15 – hard disk controller 2
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*/
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function PIC(PC, port_num) {
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function PIC(PC, port_num) {
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PC.register_ioport_write(port_num, 2, 1, this.ioport_write.bind(this));
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PC.register_ioport_write(port_num, 2, 1, this.ioport_write.bind(this));
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PC.register_ioport_read(port_num, 2, 1, this.ioport_read.bind(this));
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PC.register_ioport_read(port_num, 2, 1, this.ioport_read.bind(this));
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@ -13,9 +73,9 @@ function PIC(PC, port_num) {
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}
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}
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PIC.prototype.reset = function() {
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PIC.prototype.reset = function() {
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this.last_irr = 0;
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this.last_irr = 0;
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this.irr = 0;
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this.irr = 0; //Interrupt Request Register
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this.imr = 0;
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this.imr = 0; //Interrupt Mask Register
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this.isr = 0;
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this.isr = 0; //In-Service Register
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this.priority_add = 0;
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this.priority_add = 0;
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this.irq_base = 0;
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this.irq_base = 0;
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this.read_reg_select = 0;
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this.read_reg_select = 0;
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@ -24,54 +84,66 @@ PIC.prototype.reset = function() {
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this.auto_eoi = 0;
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this.auto_eoi = 0;
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this.rotate_on_autoeoi = 0;
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this.rotate_on_autoeoi = 0;
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this.init4 = 0;
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this.init4 = 0;
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this.elcr = 0;
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this.elcr = 0; // Edge/Level Control Register
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this.elcr_mask = 0;
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this.elcr_mask = 0;
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};
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};
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PIC.prototype.set_irq1 = function(Rg, Qf) {
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PIC.prototype.set_irq1 = function(irq, Qf) {
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var wc;
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var ir_register;
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wc = 1 << Rg;
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ir_register = 1 << irq;
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if (Qf) {
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if (Qf) {
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if ((this.last_irr & wc) == 0)
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if ((this.last_irr & ir_register) == 0)
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this.irr |= wc;
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this.irr |= ir_register;
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this.last_irr |= wc;
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this.last_irr |= ir_register;
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} else {
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} else {
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this.last_irr &= ~wc;
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this.last_irr &= ~ir_register;
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}
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}
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};
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};
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PIC.prototype.get_priority = function(wc) {
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/*
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var Sg;
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The priority assignments for IRQ0-7 seem to be maintained in a
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if (wc == 0)
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cyclic order modulo 8 by the 8259A. On bootup, it default to:
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Priority: 0 1 2 3 4 5 6 7
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IRQ: 7 6 5 4 3 2 1 0
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but can be rotated automatically or programmatically to a state e.g.:
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Priority: 5 6 7 0 1 2 3 4
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IRQ: 7 6 5 4 3 2 1 0
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*/
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PIC.prototype.get_priority = function(ir_register) {
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var priority;
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if (ir_register == 0)
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return -1;
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return -1;
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Sg = 7;
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priority = 7;
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while ((wc & (1 << ((Sg + this.priority_add) & 7))) == 0)
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while ((ir_register & (1 << ((priority + this.priority_add) & 7))) == 0)
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Sg--;
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priority--;
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return Sg;
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return priority;
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};
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};
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PIC.prototype.get_irq = function() {
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PIC.prototype.get_irq = function() {
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var wc, Tg, Sg;
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var ir_register, in_service_priority, priority;
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wc = this.irr & ~this.imr;
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ir_register = this.irr & ~this.imr;
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Sg = this.get_priority(wc);
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priority = this.get_priority(ir_register);
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if (Sg < 0)
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if (priority < 0)
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return -1;
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return -1;
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Tg = this.get_priority(this.isr);
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in_service_priority = this.get_priority(this.isr);
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if (Sg > Tg) {
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if (priority > in_service_priority) {
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return Sg;
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return priority;
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} else {
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} else {
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return -1;
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return -1;
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}
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}
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};
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};
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PIC.prototype.intack = function(Rg) {
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PIC.prototype.intack = function(irq) {
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if (this.auto_eoi) {
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if (this.auto_eoi) {
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if (this.rotate_on_auto_eoi)
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if (this.rotate_on_auto_eoi)
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this.priority_add = (Rg + 1) & 7;
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this.priority_add = (irq + 1) & 7;
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} else {
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} else {
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this.isr |= (1 << Rg);
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this.isr |= (1 << irq);
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}
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}
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if (!(this.elcr & (1 << Rg)))
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if (!(this.elcr & (1 << irq)))
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this.irr &= ~(1 << Rg);
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this.irr &= ~(1 << irq);
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};
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};
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PIC.prototype.ioport_write = function(mem8_loc, x) {
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PIC.prototype.ioport_write = function(mem8_loc, x) {
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var Sg;
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var priority;
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mem8_loc &= 1;
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mem8_loc &= 1;
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if (mem8_loc == 0) {
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if (mem8_loc == 0) {
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if (x & 0x10) {
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if (x & 0x10) {
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@ -105,9 +177,9 @@ PIC.prototype.ioport_write = function(mem8_loc, x) {
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break;
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break;
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case 0x20:
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case 0x20:
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case 0xa0:
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case 0xa0:
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Sg = this.get_priority(this.isr);
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priority = this.get_priority(this.isr);
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if (Sg >= 0) {
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if (priority >= 0) {
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this.isr &= ~(1 << ((Sg + this.priority_add) & 7));
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this.isr &= ~(1 << ((priority + this.priority_add) & 7));
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}
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}
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if (x == 0xa0)
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if (x == 0xa0)
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this.priority_add = (this.priority_add + 1) & 7;
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this.priority_add = (this.priority_add + 1) & 7;
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@ -120,8 +192,8 @@ PIC.prototype.ioport_write = function(mem8_loc, x) {
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case 0x65:
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case 0x65:
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case 0x66:
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case 0x66:
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case 0x67:
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case 0x67:
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Sg = x & 7;
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priority = x & 7;
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this.isr &= ~(1 << Sg);
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this.isr &= ~(1 << priority);
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break;
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break;
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case 0xc0:
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case 0xc0:
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case 0xc1:
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case 0xc1:
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@ -141,9 +213,9 @@ PIC.prototype.ioport_write = function(mem8_loc, x) {
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case 0xe5:
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case 0xe5:
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case 0xe6:
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case 0xe6:
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case 0xe7:
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case 0xe7:
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Sg = x & 7;
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priority = x & 7;
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this.isr &= ~(1 << Sg);
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this.isr &= ~(1 << priority);
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this.priority_add = (Sg + 1) & 7;
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this.priority_add = (priority + 1) & 7;
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break;
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break;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -172,69 +244,69 @@ PIC.prototype.ioport_write = function(mem8_loc, x) {
|
|||||||
}
|
}
|
||||||
};
|
};
|
||||||
PIC.prototype.ioport_read = function(Ug) {
|
PIC.prototype.ioport_read = function(Ug) {
|
||||||
var mem8_loc, Pg;
|
var mem8_loc, return_register;
|
||||||
mem8_loc = Ug & 1;
|
mem8_loc = Ug & 1;
|
||||||
if (mem8_loc == 0) {
|
if (mem8_loc == 0) {
|
||||||
if (this.read_reg_select)
|
if (this.read_reg_select)
|
||||||
Pg = this.isr;
|
return_register = this.isr;
|
||||||
else
|
else
|
||||||
Pg = this.irr;
|
return_register = this.irr;
|
||||||
} else {
|
} else {
|
||||||
Pg = this.imr;
|
return_register = this.imr;
|
||||||
}
|
}
|
||||||
return Pg;
|
return return_register;
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
function PIC_Controller(PC, Wg, Ug, Xg) {
|
function PIC_Controller(PC, master_PIC_port, slave_PIC_port, cpu_set_irq_callback) {
|
||||||
this.pics = new Array();
|
this.pics = new Array();
|
||||||
this.pics[0] = new PIC(PC, Wg);
|
this.pics[0] = new PIC(PC, master_PIC_port);
|
||||||
this.pics[1] = new PIC(PC, Ug);
|
this.pics[1] = new PIC(PC, slave_PIC_port);
|
||||||
this.pics[0].elcr_mask = 0xf8;
|
this.pics[0].elcr_mask = 0xf8;
|
||||||
this.pics[1].elcr_mask = 0xde;
|
this.pics[1].elcr_mask = 0xde;
|
||||||
this.irq_requested = 0;
|
this.irq_requested = 0;
|
||||||
this.cpu_set_irq = Xg;
|
this.cpu_set_irq = cpu_set_irq_callback;
|
||||||
this.pics[0].update_irq = this.update_irq.bind(this);
|
this.pics[0].update_irq = this.update_irq.bind(this);
|
||||||
this.pics[1].update_irq = this.update_irq.bind(this);
|
this.pics[1].update_irq = this.update_irq.bind(this);
|
||||||
}
|
}
|
||||||
PIC_Controller.prototype.update_irq = function() {
|
PIC_Controller.prototype.update_irq = function() {
|
||||||
var Yg, Rg;
|
var slave_irq, irq;
|
||||||
Yg = this.pics[1].get_irq();
|
slave_irq = this.pics[1].get_irq();
|
||||||
if (Yg >= 0) {
|
if (slave_irq >= 0) {
|
||||||
this.pics[0].set_irq1(2, 1);
|
this.pics[0].set_irq1(2, 1);
|
||||||
this.pics[0].set_irq1(2, 0);
|
this.pics[0].set_irq1(2, 0);
|
||||||
}
|
}
|
||||||
Rg = this.pics[0].get_irq();
|
irq = this.pics[0].get_irq();
|
||||||
if (Rg >= 0) {
|
if (irq >= 0) {
|
||||||
this.cpu_set_irq(1);
|
this.cpu_set_irq(1);
|
||||||
} else {
|
} else {
|
||||||
this.cpu_set_irq(0);
|
this.cpu_set_irq(0);
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
PIC_Controller.prototype.set_irq = function(Rg, Qf) {
|
PIC_Controller.prototype.set_irq = function(irq, Qf) {
|
||||||
this.pics[Rg >> 3].set_irq1(Rg & 7, Qf);
|
this.pics[irq >> 3].set_irq1(irq & 7, Qf);
|
||||||
this.update_irq();
|
this.update_irq();
|
||||||
};
|
};
|
||||||
PIC_Controller.prototype.get_hard_intno = function() {
|
PIC_Controller.prototype.get_hard_intno = function() {
|
||||||
var Rg, Yg, intno;
|
var irq, slave_irq, intno;
|
||||||
Rg = this.pics[0].get_irq();
|
irq = this.pics[0].get_irq();
|
||||||
if (Rg >= 0) {
|
if (irq >= 0) {
|
||||||
this.pics[0].intack(Rg);
|
this.pics[0].intack(irq);
|
||||||
if (Rg == 2) {
|
if (irq == 2) { //IRQ 2 cascaded to slave 8259 INT line in PC/AT
|
||||||
Yg = this.pics[1].get_irq();
|
slave_irq = this.pics[1].get_irq();
|
||||||
if (Yg >= 0) {
|
if (slave_irq >= 0) {
|
||||||
this.pics[1].intack(Yg);
|
this.pics[1].intack(slave_irq);
|
||||||
} else {
|
} else {
|
||||||
Yg = 7;
|
slave_irq = 7;
|
||||||
}
|
}
|
||||||
intno = this.pics[1].irq_base + Yg;
|
intno = this.pics[1].irq_base + slave_irq;
|
||||||
Rg = Yg + 8;
|
irq = slave_irq + 8;
|
||||||
} else {
|
} else {
|
||||||
intno = this.pics[0].irq_base + Rg;
|
intno = this.pics[0].irq_base + irq;
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
Rg = 7;
|
irq = 7;
|
||||||
intno = this.pics[0].irq_base + Rg;
|
intno = this.pics[0].irq_base + irq;
|
||||||
}
|
}
|
||||||
this.update_irq();
|
this.update_irq();
|
||||||
return intno;
|
return intno;
|
||||||
|
54
PIT.js
54
PIT.js
@ -1,23 +1,27 @@
|
|||||||
/*
|
/*
|
||||||
JSLinux-deobfuscated - An annotated version of the original JSLinux.
|
JSLinux-deobfuscated - An annotated version of the original JSLinux.
|
||||||
|
|
||||||
Original is Copyright (c) 2011-2012 Fabrice Bellard
|
Original is Copyright (c) 2011-2012 Fabrice Bellard
|
||||||
Redistribution or commercial use is prohibited without the author's permission.
|
Redistribution or commercial use is prohibited without the author's permission.
|
||||||
|
|
||||||
8254 Programmble Interrupt Timer Emulator
|
8254 Programmble Interrupt Timer Emulator
|
||||||
|
|
||||||
|
Useful References
|
||||||
|
-----------------
|
||||||
|
https://en.wikipedia.org/wiki/Intel_8253
|
||||||
*/
|
*/
|
||||||
function PIT(PC, ah, bh) {
|
function PIT(PC, set_irq_callback, cycle_count_callback) {
|
||||||
var s, i;
|
var s, i;
|
||||||
this.pit_channels = new Array();
|
this.pit_channels = new Array();
|
||||||
for (i = 0; i < 3; i++) {
|
for (i = 0; i < 3; i++) {
|
||||||
s = new IRQCH(bh);
|
s = new IRQCH(cycle_count_callback);
|
||||||
this.pit_channels[i] = s;
|
this.pit_channels[i] = s;
|
||||||
s.mode = 3;
|
s.mode = 3;
|
||||||
s.gate = (i != 2) >> 0;
|
s.gate = (i != 2) >> 0;
|
||||||
s.pit_load_count(0);
|
s.pit_load_count(0);
|
||||||
}
|
}
|
||||||
this.speaker_data_on = 0;
|
this.speaker_data_on = 0;
|
||||||
this.set_irq = ah;
|
this.set_irq = set_irq_callback;
|
||||||
// Ports:
|
// Ports:
|
||||||
// 0x40: Channel 0 data port
|
// 0x40: Channel 0 data port
|
||||||
// 0x61: Control
|
// 0x61: Control
|
||||||
@ -27,9 +31,7 @@ function PIT(PC, ah, bh) {
|
|||||||
PC.register_ioport_write(0x61, 1, 1, this.speaker_ioport_write.bind(this));
|
PC.register_ioport_write(0x61, 1, 1, this.speaker_ioport_write.bind(this));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
function IRQCH(cycle_count_callback) {
|
||||||
|
|
||||||
function IRQCH(bh) {
|
|
||||||
this.count = 0;
|
this.count = 0;
|
||||||
this.latched_count = 0;
|
this.latched_count = 0;
|
||||||
this.rw_state = 0;
|
this.rw_state = 0;
|
||||||
@ -37,7 +39,7 @@ function IRQCH(bh) {
|
|||||||
this.bcd = 0;
|
this.bcd = 0;
|
||||||
this.gate = 0;
|
this.gate = 0;
|
||||||
this.count_load_time = 0;
|
this.count_load_time = 0;
|
||||||
this.get_ticks = bh;
|
this.get_ticks = cycle_count_callback;
|
||||||
this.pit_time_unit = 1193182 / 2000000;
|
this.pit_time_unit = 1193182 / 2000000;
|
||||||
}
|
}
|
||||||
IRQCH.prototype.get_time = function() {
|
IRQCH.prototype.get_time = function() {
|
||||||
@ -64,29 +66,23 @@ IRQCH.prototype.pit_get_out = function() {
|
|||||||
d = this.get_time() - this.count_load_time;
|
d = this.get_time() - this.count_load_time;
|
||||||
switch (this.mode) {
|
switch (this.mode) {
|
||||||
default:
|
default:
|
||||||
// Interrupt on terminal count
|
case 0: // Interrupt on terminal count
|
||||||
case 0:
|
|
||||||
eh = (d >= this.count) >> 0;
|
eh = (d >= this.count) >> 0;
|
||||||
break;
|
break;
|
||||||
// One shot
|
case 1: // One shot
|
||||||
case 1:
|
|
||||||
eh = (d < this.count) >> 0;
|
eh = (d < this.count) >> 0;
|
||||||
break;
|
break;
|
||||||
// Frequency divider
|
case 2: // Frequency divider
|
||||||
case 2:
|
|
||||||
if ((d % this.count) == 0 && d != 0)
|
if ((d % this.count) == 0 && d != 0)
|
||||||
eh = 1;
|
eh = 1;
|
||||||
else
|
else
|
||||||
eh = 0;
|
eh = 0;
|
||||||
break;
|
break;
|
||||||
// Square wave
|
case 3: // Square wave
|
||||||
case 3:
|
|
||||||
eh = ((d % this.count) < (this.count >> 1)) >> 0;
|
eh = ((d % this.count) < (this.count >> 1)) >> 0;
|
||||||
break;
|
break;
|
||||||
// SW strobe
|
case 4: // SW strobe
|
||||||
case 4:
|
case 5: // HW strobe
|
||||||
// HW strobe
|
|
||||||
case 5:
|
|
||||||
eh = (d == this.count) >> 0;
|
eh = (d == this.count) >> 0;
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -97,21 +93,21 @@ IRQCH.prototype.get_next_transition_time = function() {
|
|||||||
d = this.get_time() - this.count_load_time;
|
d = this.get_time() - this.count_load_time;
|
||||||
switch (this.mode) {
|
switch (this.mode) {
|
||||||
default:
|
default:
|
||||||
case 0:
|
case 0: // Interrupt on terminal count
|
||||||
case 1:
|
case 1: // One shot
|
||||||
if (d < this.count)
|
if (d < this.count)
|
||||||
fh = this.count;
|
fh = this.count;
|
||||||
else
|
else
|
||||||
return -1;
|
return -1;
|
||||||
break;
|
break;
|
||||||
case 2:
|
case 2: // Frequency divider
|
||||||
base = (d / this.count) * this.count;
|
base = (d / this.count) * this.count;
|
||||||
if ((d - base) == 0 && d != 0)
|
if ((d - base) == 0 && d != 0)
|
||||||
fh = base + this.count;
|
fh = base + this.count;
|
||||||
else
|
else
|
||||||
fh = base + this.count + 1;
|
fh = base + this.count + 1;
|
||||||
break;
|
break;
|
||||||
case 3:
|
case 3: // Square wave
|
||||||
base = (d / this.count) * this.count;
|
base = (d / this.count) * this.count;
|
||||||
gh = ((this.count + 1) >> 1);
|
gh = ((this.count + 1) >> 1);
|
||||||
if ((d - base) < gh)
|
if ((d - base) < gh)
|
||||||
@ -119,8 +115,8 @@ IRQCH.prototype.get_next_transition_time = function() {
|
|||||||
else
|
else
|
||||||
fh = base + this.count;
|
fh = base + this.count;
|
||||||
break;
|
break;
|
||||||
case 4:
|
case 4: // SW strobe
|
||||||
case 5:
|
case 5: // HW strobe
|
||||||
if (d < this.count)
|
if (d < this.count)
|
||||||
fh = this.count;
|
fh = this.count;
|
||||||
else if (d == this.count)
|
else if (d == this.count)
|
||||||
|
Loading…
Reference in New Issue
Block a user